Changes: - Clean up and re-work Surface Aggregator Module support for the Surface Pro 8. - Fix a bug causing time-outs when unloading drivers of detached Surface Aggregator Module devices such as contained in the Surface Book 3 base and the Surface Pro 8 keyboard cover. - Move Surface Aggregator devices of the Surface Book 3 base from the base hub to the KIP hub introduced for the Surface Pro 8. Links: - kernel:e716df100b
- SAM:3cfb0b76c8
293 lines
9.1 KiB
Diff
293 lines
9.1 KiB
Diff
From e291fe440d5f7447c3f81ee223c9923423b45aac Mon Sep 17 00:00:00 2001
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From: Sachi King <nakato@nakato.io>
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Date: Sat, 29 May 2021 17:47:38 +1000
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Subject: [PATCH] ACPI: Add quirk for Surface Laptop 4 AMD missing irq 7
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override
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This patch is the work of Thomas Gleixner <tglx@linutronix.de> and is
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copied from:
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https://lore.kernel.org/lkml/87lf8ddjqx.ffs@nanos.tec.linutronix.de/
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This patch adds a quirk to the ACPI setup to patch in the the irq 7 pin
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setup that is missing in the laptops ACPI table.
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This patch was used for validation of the issue, and is not a proper
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fix, but is probably a better temporary hack than continuing to probe
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the Legacy PIC and run with the PIC in an unknown state.
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Patchset: amd-gpio
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---
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arch/x86/kernel/acpi/boot.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
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index e55e0c1fad8c..46dfad41b401 100644
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--- a/arch/x86/kernel/acpi/boot.c
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+++ b/arch/x86/kernel/acpi/boot.c
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@@ -22,6 +22,7 @@
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#include <linux/efi-bgrt.h>
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#include <linux/serial_core.h>
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#include <linux/pgtable.h>
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+#include <linux/dmi.h>
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#include <asm/e820/api.h>
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#include <asm/irqdomain.h>
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@@ -1143,6 +1144,17 @@ static void __init mp_config_acpi_legacy_irqs(void)
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}
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}
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+static const struct dmi_system_id surface_quirk[] __initconst = {
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+ {
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+ .ident = "Microsoft Surface Laptop 4 (AMD)",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
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+ DMI_MATCH(DMI_PRODUCT_SKU, "Surface_Laptop_4_1952:1953")
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+ },
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+ },
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+ {}
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+};
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+
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/*
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* Parse IOAPIC related entries in MADT
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* returns 0 on success, < 0 on error
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@@ -1198,6 +1210,11 @@ static int __init acpi_parse_madt_ioapic_entries(void)
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acpi_sci_ioapic_setup(acpi_gbl_FADT.sci_interrupt, 0, 0,
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acpi_gbl_FADT.sci_interrupt);
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+ if (dmi_check_system(surface_quirk)) {
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+ pr_warn("Surface hack: Override irq 7\n");
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+ mp_override_legacy_irq(7, 3, 3, 7);
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+ }
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+
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/* Fill in identity legacy mappings where no override */
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mp_config_acpi_legacy_irqs();
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--
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2.33.1
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From 8d5024b44c7cd6819b7deca883ee4b0f79917b30 Mon Sep 17 00:00:00 2001
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From: Maximilian Luz <luzmaximilian@gmail.com>
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Date: Thu, 3 Jun 2021 14:04:26 +0200
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Subject: [PATCH] ACPI: Add AMD 13" Surface Laptop 4 model to irq 7 override
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quirk
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The 13" version of the Surface Laptop 4 has the same problem as the 15"
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version, but uses a different SKU. Add that SKU to the quirk as well.
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Patchset: amd-gpio
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---
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arch/x86/kernel/acpi/boot.c | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
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index 46dfad41b401..78bf6a097dc5 100644
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--- a/arch/x86/kernel/acpi/boot.c
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+++ b/arch/x86/kernel/acpi/boot.c
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@@ -1146,12 +1146,19 @@ static void __init mp_config_acpi_legacy_irqs(void)
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static const struct dmi_system_id surface_quirk[] __initconst = {
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{
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- .ident = "Microsoft Surface Laptop 4 (AMD)",
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+ .ident = "Microsoft Surface Laptop 4 (AMD 15\")",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
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DMI_MATCH(DMI_PRODUCT_SKU, "Surface_Laptop_4_1952:1953")
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},
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},
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+ {
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+ .ident = "Microsoft Surface Laptop 4 (AMD 13\")",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
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+ DMI_MATCH(DMI_PRODUCT_SKU, "Surface_Laptop_4_1958:1959")
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+ },
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+ },
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{}
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};
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--
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2.33.1
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From 9695d8c770fbff8b00f3a6fea1f612bbb095cd6a Mon Sep 17 00:00:00 2001
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From: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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Date: Tue, 31 Aug 2021 17:36:12 +0530
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Subject: [PATCH] pinctrl: amd: Add irq field data
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pinctrl_amd use gpiochip_get_data() to get their local state containers
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back from the gpiochip passed as amd_gpio chip data.
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Hence added irq field data to get directly using amd_gpio chip data.
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Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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Patchset: amd-gpio
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---
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drivers/pinctrl/pinctrl-amd.c | 9 ++++-----
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drivers/pinctrl/pinctrl-amd.h | 1 +
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2 files changed, 5 insertions(+), 5 deletions(-)
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diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
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index 5b764740b829..79b8b7f91996 100644
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--- a/drivers/pinctrl/pinctrl-amd.c
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+++ b/drivers/pinctrl/pinctrl-amd.c
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@@ -904,7 +904,6 @@ static struct pinctrl_desc amd_pinctrl_desc = {
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static int amd_gpio_probe(struct platform_device *pdev)
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{
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int ret = 0;
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- int irq_base;
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struct resource *res;
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struct amd_gpio *gpio_dev;
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struct gpio_irq_chip *girq;
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@@ -927,9 +926,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
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if (!gpio_dev->base)
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return -ENOMEM;
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- irq_base = platform_get_irq(pdev, 0);
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- if (irq_base < 0)
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- return irq_base;
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+ gpio_dev->irq = platform_get_irq(pdev, 0);
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+ if (gpio_dev->irq < 0)
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+ return gpio_dev->irq;
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#ifdef CONFIG_PM_SLEEP
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gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
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@@ -989,7 +988,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
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goto out2;
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}
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- ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
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+ ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
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IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
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if (ret)
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goto out2;
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diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
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index 95e763424042..1d4317073654 100644
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--- a/drivers/pinctrl/pinctrl-amd.h
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+++ b/drivers/pinctrl/pinctrl-amd.h
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@@ -98,6 +98,7 @@ struct amd_gpio {
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struct resource *res;
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struct platform_device *pdev;
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u32 *saved_regs;
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+ int irq;
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};
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/* KERNCZ configuration*/
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--
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2.33.1
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From 3e0af5b7739aecbe646104171bdcefb925c4cc6d Mon Sep 17 00:00:00 2001
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From: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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Date: Tue, 31 Aug 2021 17:36:13 +0530
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Subject: [PATCH] pinctrl: amd: Handle wake-up interrupt
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Enable/disable power management wakeup mode, which is disabled by
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default. enable_irq_wake enables wakes the system from sleep.
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Hence added enable/disable irq_wake to handle wake-up interrupt.
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Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
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Patchset: amd-gpio
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---
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drivers/pinctrl/pinctrl-amd.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
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index 79b8b7f91996..d19974aceb2e 100644
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--- a/drivers/pinctrl/pinctrl-amd.c
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+++ b/drivers/pinctrl/pinctrl-amd.c
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@@ -445,6 +445,7 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
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+ int err;
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raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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@@ -457,6 +458,15 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ if (on)
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+ err = enable_irq_wake(gpio_dev->irq);
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+ else
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+ err = disable_irq_wake(gpio_dev->irq);
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+
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+ if (err)
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+ dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
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+ on ? "enable" : "disable");
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+
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return 0;
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}
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--
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2.33.1
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From 6567cde21a9e1cbf952eedfd293ef72f6cfe55b6 Mon Sep 17 00:00:00 2001
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From: Sachi King <nakato@nakato.io>
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Date: Fri, 1 Oct 2021 21:19:09 +1000
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Subject: [PATCH] pinctrl: amd: disable and mask interrupts on probe
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Some systems such as the Microsoft Surface Laptop 4 leave interrupts
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enabled and configured for use in sleep states on boot, which cause
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unexpected behaviour such as spurious wakes and failed resumes in
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s2idle states.
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As interrupts should not be enabled until they are claimed and
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explicitly enabled, disabling any interrupts mistakenly left enabled by
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firmware should be safe.
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Signed-off-by: Sachi King <nakato@nakato.io>
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Patchset: amd-gpio
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---
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drivers/pinctrl/pinctrl-amd.c | 29 +++++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
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index d19974aceb2e..d32daf1c862f 100644
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--- a/drivers/pinctrl/pinctrl-amd.c
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+++ b/drivers/pinctrl/pinctrl-amd.c
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@@ -842,6 +842,32 @@ static const struct pinconf_ops amd_pinconf_ops = {
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.pin_config_group_set = amd_pinconf_group_set,
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};
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+static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) {
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+ struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
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+ unsigned long flags;
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+ u32 pin_reg, mask;
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+ int i;
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+
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+ mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3)
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+ | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF)
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+ | BIT(INTERRUPT_MASK_OFF) | BIT(WAKE_CNTRL_OFF_S4);
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+
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+ for (i = 0; i < desc->npins; i++) {
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+ int pin = desc->pins[i].number;
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+ const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
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+ if (!pd)
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+ continue;
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+
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+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
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+
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+ pin_reg = readl(gpio_dev->base + i * 4);
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+ pin_reg &= ~mask;
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+ writel(pin_reg, gpio_dev->base + i * 4);
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+
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+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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+ }
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+}
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+
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#ifdef CONFIG_PM_SLEEP
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static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
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{
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@@ -978,6 +1004,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
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return PTR_ERR(gpio_dev->pctrl);
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}
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+ /* Disable and mask interrupts */
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+ amd_gpio_irq_init(gpio_dev);
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+
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girq = &gpio_dev->gc.irq;
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girq->chip = &amd_gpio_irqchip;
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/* This will let us handle the parent IRQ in the driver */
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--
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2.33.1
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