240 lines
5 KiB
C
240 lines
5 KiB
C
/*
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* Corenet based SoC DS Setup
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/pgtable.h>
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#include <asm/ppc-pci.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/ehv_pic.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "smp.h"
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#include "mpc85xx.h"
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void __init corenet_gen_pic_init(void)
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{
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struct mpic *mpic;
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unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
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MPIC_NO_RESET;
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struct device_node *np;
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if (ppc_md.get_irq == mpic_get_coreint_irq)
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flags |= MPIC_ENABLE_COREINT;
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mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (np) {
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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of_node_put(np);
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}
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}
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/*
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* Setup the architecture
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*/
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void __init corenet_gen_setup_arch(void)
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{
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mpc85xx_smp_init();
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swiotlb_detect_4g();
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#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
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/*
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* Inbound windows don't cover the full lower 4 GiB
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* due to conflicts with PCICSRBAR and outbound windows,
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* so limit the DMA32 zone to 2 GiB, to allow consistent
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* allocations to succeed.
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*/
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limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
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#endif
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pr_info("%s board\n", ppc_md.name);
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mpc85xx_qe_init();
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}
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static const struct of_device_id of_device_ids[] = {
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{
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.compatible = "simple-bus"
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},
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{
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.compatible = "mdio-mux-gpio"
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},
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{
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.compatible = "fsl,fpga-ngpixis"
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},
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{
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.compatible = "fsl,fpga-qixis"
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},
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{
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.compatible = "fsl,srio",
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},
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{
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.compatible = "fsl,p4080-pcie",
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},
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{
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.compatible = "fsl,qoriq-pcie-v2.2",
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},
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{
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.compatible = "fsl,qoriq-pcie-v2.3",
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},
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{
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.compatible = "fsl,qoriq-pcie-v2.4",
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},
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{
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.compatible = "fsl,qoriq-pcie-v3.0",
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},
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{
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.compatible = "fsl,qe",
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},
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/* The following two are for the Freescale hypervisor */
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{
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.name = "hypervisor",
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},
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{
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.name = "handles",
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},
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{}
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};
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int __init corenet_gen_publish_devices(void)
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{
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return of_platform_bus_probe(NULL, of_device_ids, NULL);
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}
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static const char * const boards[] __initconst = {
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"fsl,P2041RDB",
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"fsl,P3041DS",
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"fsl,OCA4080",
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"fsl,P4080DS",
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"fsl,P5020DS",
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"fsl,P5040DS",
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"fsl,T2080QDS",
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"fsl,T2080RDB",
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"fsl,T2081QDS",
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"fsl,T4240QDS",
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"fsl,T4240RDB",
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"fsl,B4860QDS",
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"fsl,B4420QDS",
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"fsl,B4220QDS",
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"fsl,T1023RDB",
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"fsl,T1024QDS",
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"fsl,T1024RDB",
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"fsl,T1040D4RDB",
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"fsl,T1042D4RDB",
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"fsl,T1040QDS",
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"fsl,T1042QDS",
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"fsl,T1040RDB",
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"fsl,T1042RDB",
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"fsl,T1042RDB_PI",
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"keymile,kmcent2",
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"keymile,kmcoge4",
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"varisys,CYRUS",
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NULL
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};
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init corenet_generic_probe(void)
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{
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char hv_compat[24];
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int i;
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#ifdef CONFIG_SMP
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extern struct smp_ops_t smp_85xx_ops;
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#endif
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if (of_device_compatible_match(of_root, boards))
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return 1;
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/* Check if we're running under the Freescale hypervisor */
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for (i = 0; boards[i]; i++) {
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snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
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if (of_machine_is_compatible(hv_compat)) {
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ppc_md.init_IRQ = ehv_pic_init;
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ppc_md.get_irq = ehv_pic_get_irq;
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ppc_md.restart = fsl_hv_restart;
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pm_power_off = fsl_hv_halt;
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ppc_md.halt = fsl_hv_halt;
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#ifdef CONFIG_SMP
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/*
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* Disable the timebase sync operations because we
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* can't write to the timebase registers under the
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* hypervisor.
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*/
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smp_85xx_ops.give_timebase = NULL;
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smp_85xx_ops.take_timebase = NULL;
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#endif
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return 1;
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}
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}
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return 0;
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}
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define_machine(corenet_generic) {
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.name = "CoreNet Generic",
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.probe = corenet_generic_probe,
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.setup_arch = corenet_gen_setup_arch,
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.init_IRQ = corenet_gen_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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/*
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* Core reset may cause issues if using the proxy mode of MPIC.
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* So, use the mixed mode of MPIC if enabling CPU hotplug.
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*
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* Likewise, problems have been seen with kexec when coreint is enabled.
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*/
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
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.get_irq = mpic_get_irq,
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#else
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.get_irq = mpic_get_coreint_irq,
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#endif
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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#ifdef CONFIG_PPC64
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.power_save = book3e_idle,
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#else
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.power_save = e500_idle,
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#endif
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};
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machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
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#ifdef CONFIG_SWIOTLB
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machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
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#endif
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