633 lines
19 KiB
C
633 lines
19 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "intel_drv.h"
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#define CTM_COEFF_SIGN (1ULL << 63)
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#define CTM_COEFF_1_0 (1ULL << 32)
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#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
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#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
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#define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
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#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
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#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
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#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
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#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
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#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
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#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
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#define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
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/*
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* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
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* format). This macro takes the coefficient we want transformed and the
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* number of fractional bits.
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*
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* We only have a 9 bits precision window which slides depending on the value
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* of the CTM coefficient and we write the value from bit 3. We also round the
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* value.
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*/
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#define I9XX_CSC_COEFF_FP(coeff, fbits) \
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(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
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#define I9XX_CSC_COEFF_LIMITED_RANGE \
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I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
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#define I9XX_CSC_COEFF_1_0 \
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((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
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static bool crtc_state_is_legacy(struct drm_crtc_state *state)
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{
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return !state->degamma_lut &&
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!state->ctm &&
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state->gamma_lut &&
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state->gamma_lut->length == LEGACY_LUT_LENGTH;
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}
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/*
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* When using limited range, multiply the matrix given by userspace by
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* the matrix that we would use for the limited range. We do the
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* multiplication in U2.30 format.
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*/
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static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
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{
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int i;
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for (i = 0; i < 9; i++)
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result[i] = 0;
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for (i = 0; i < 3; i++) {
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int64_t user_coeff = input[i * 3 + i];
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uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2;
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uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff),
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0,
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CTM_COEFF_4_0 - 1) >> 2;
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result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27;
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if (CTM_COEFF_NEGATIVE(user_coeff))
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result[i * 3 + i] |= CTM_COEFF_SIGN;
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}
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}
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/* Set up the pipe CSC unit. */
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static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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{
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struct drm_crtc *crtc = crtc_state->crtc;
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int i, pipe = intel_crtc->pipe;
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uint16_t coeffs[9] = { 0, };
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struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
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if (crtc_state->ctm) {
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struct drm_color_ctm *ctm =
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(struct drm_color_ctm *)crtc_state->ctm->data;
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uint64_t input[9] = { 0, };
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if (intel_crtc_state->limited_color_range) {
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ctm_mult_by_limited(input, ctm->matrix);
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} else {
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for (i = 0; i < ARRAY_SIZE(input); i++)
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input[i] = ctm->matrix[i];
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}
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/*
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* Convert fixed point S31.32 input to format supported by the
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* hardware.
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*/
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for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
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uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
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/*
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* Clamp input value to min/max supported by
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* hardware.
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*/
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abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
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/* sign bit */
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if (CTM_COEFF_NEGATIVE(input[i]))
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coeffs[i] |= 1 << 15;
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if (abs_coeff < CTM_COEFF_0_125)
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coeffs[i] |= (3 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 12);
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else if (abs_coeff < CTM_COEFF_0_25)
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coeffs[i] |= (2 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 11);
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else if (abs_coeff < CTM_COEFF_0_5)
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coeffs[i] |= (1 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 10);
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else if (abs_coeff < CTM_COEFF_1_0)
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coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
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else if (abs_coeff < CTM_COEFF_2_0)
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coeffs[i] |= (7 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 8);
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else
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coeffs[i] |= (6 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 7);
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}
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} else {
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/*
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* Load an identity matrix if no coefficients are provided.
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*
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* TODO: Check what kind of values actually come out of the
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* pipe with these coeff/postoff values and adjust to get the
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* best accuracy. Perhaps we even need to take the bpc value
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* into consideration.
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*/
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for (i = 0; i < 3; i++) {
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if (intel_crtc_state->limited_color_range)
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coeffs[i * 3 + i] =
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I9XX_CSC_COEFF_LIMITED_RANGE;
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else
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coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
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}
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}
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I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
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I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
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I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
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I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
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I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
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I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
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I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
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if (INTEL_GEN(dev_priv) > 6) {
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uint16_t postoff = 0;
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if (intel_crtc_state->limited_color_range)
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postoff = (16 * (1 << 12) / 255) & 0x1fff;
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I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
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I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
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I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
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I915_WRITE(PIPE_CSC_MODE(pipe), 0);
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} else {
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uint32_t mode = CSC_MODE_YUV_TO_RGB;
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if (intel_crtc_state->limited_color_range)
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mode |= CSC_BLACK_SCREEN_OFFSET;
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I915_WRITE(PIPE_CSC_MODE(pipe), mode);
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}
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}
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/*
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* Set up the pipe CSC unit on CherryView.
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*/
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static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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int pipe = to_intel_crtc(crtc)->pipe;
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uint32_t mode;
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if (state->ctm) {
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struct drm_color_ctm *ctm =
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(struct drm_color_ctm *) state->ctm->data;
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uint16_t coeffs[9] = { 0, };
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int i;
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for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
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uint64_t abs_coeff =
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((1ULL << 63) - 1) & ctm->matrix[i];
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/* Round coefficient. */
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abs_coeff += 1 << (32 - 13);
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/* Clamp to hardware limits. */
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abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
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/* Write coefficients in S3.12 format. */
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if (ctm->matrix[i] & (1ULL << 63))
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coeffs[i] = 1 << 15;
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coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
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coeffs[i] |= (abs_coeff >> 20) & 0xfff;
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}
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I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
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coeffs[1] << 16 | coeffs[0]);
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I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
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coeffs[3] << 16 | coeffs[2]);
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I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
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coeffs[5] << 16 | coeffs[4]);
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I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
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coeffs[7] << 16 | coeffs[6]);
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I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
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}
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mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
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if (!crtc_state_is_legacy(state)) {
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mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
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(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
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}
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I915_WRITE(CGM_PIPE_MODE(pipe), mode);
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}
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void intel_color_set_csc(struct drm_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (dev_priv->display.load_csc_matrix)
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dev_priv->display.load_csc_matrix(crtc_state);
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}
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/* Loads the legacy palette/gamma unit for the CRTC. */
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static void i9xx_load_luts_internal(struct drm_crtc *crtc,
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struct drm_property_blob *blob,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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int i;
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if (HAS_GMCH_DISPLAY(dev_priv)) {
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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}
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if (blob) {
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struct drm_color_lut *lut = (struct drm_color_lut *) blob->data;
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for (i = 0; i < 256; i++) {
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uint32_t word =
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(drm_color_lut_extract(lut[i].red, 8) << 16) |
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(drm_color_lut_extract(lut[i].green, 8) << 8) |
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drm_color_lut_extract(lut[i].blue, 8);
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if (HAS_GMCH_DISPLAY(dev_priv))
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I915_WRITE(PALETTE(pipe, i), word);
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else
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I915_WRITE(LGC_PALETTE(pipe, i), word);
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}
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} else {
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for (i = 0; i < 256; i++) {
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uint32_t word = (i << 16) | (i << 8) | i;
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if (HAS_GMCH_DISPLAY(dev_priv))
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I915_WRITE(PALETTE(pipe, i), word);
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else
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I915_WRITE(LGC_PALETTE(pipe, i), word);
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}
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}
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}
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static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
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{
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i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
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to_intel_crtc_state(crtc_state));
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}
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/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
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static void haswell_load_luts(struct drm_crtc_state *crtc_state)
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{
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struct drm_crtc *crtc = crtc_state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *intel_crtc_state =
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to_intel_crtc_state(crtc_state);
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bool reenable_ips = false;
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/*
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* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*/
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if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
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(intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
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hsw_disable_ips(intel_crtc);
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reenable_ips = true;
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}
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intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
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I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
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i9xx_load_luts(crtc_state);
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if (reenable_ips)
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hsw_enable_ips(intel_crtc);
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}
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static void bdw_load_degamma_lut(struct drm_crtc_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
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enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
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uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
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I915_WRITE(PREC_PAL_INDEX(pipe),
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PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
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if (state->degamma_lut) {
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struct drm_color_lut *lut =
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(struct drm_color_lut *) state->degamma_lut->data;
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for (i = 0; i < lut_size; i++) {
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uint32_t word =
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drm_color_lut_extract(lut[i].red, 10) << 20 |
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drm_color_lut_extract(lut[i].green, 10) << 10 |
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drm_color_lut_extract(lut[i].blue, 10);
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I915_WRITE(PREC_PAL_DATA(pipe), word);
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}
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} else {
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for (i = 0; i < lut_size; i++) {
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uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
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I915_WRITE(PREC_PAL_DATA(pipe),
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(v << 20) | (v << 10) | v);
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}
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}
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}
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static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
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{
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struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
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enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
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uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
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WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
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I915_WRITE(PREC_PAL_INDEX(pipe),
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(offset ? PAL_PREC_SPLIT_MODE : 0) |
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PAL_PREC_AUTO_INCREMENT |
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offset);
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if (state->gamma_lut) {
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struct drm_color_lut *lut =
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(struct drm_color_lut *) state->gamma_lut->data;
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for (i = 0; i < lut_size; i++) {
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uint32_t word =
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(drm_color_lut_extract(lut[i].red, 10) << 20) |
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(drm_color_lut_extract(lut[i].green, 10) << 10) |
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drm_color_lut_extract(lut[i].blue, 10);
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I915_WRITE(PREC_PAL_DATA(pipe), word);
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}
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/* Program the max register to clamp values > 1.0. */
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
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drm_color_lut_extract(lut[i].red, 16));
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
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drm_color_lut_extract(lut[i].green, 16));
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
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drm_color_lut_extract(lut[i].blue, 16));
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} else {
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for (i = 0; i < lut_size; i++) {
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uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
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I915_WRITE(PREC_PAL_DATA(pipe),
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(v << 20) | (v << 10) | v);
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}
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
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I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
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}
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}
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/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
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static void broadwell_load_luts(struct drm_crtc_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
|
|
struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
|
|
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
|
|
|
|
if (crtc_state_is_legacy(state)) {
|
|
haswell_load_luts(state);
|
|
return;
|
|
}
|
|
|
|
bdw_load_degamma_lut(state);
|
|
bdw_load_gamma_lut(state,
|
|
INTEL_INFO(dev_priv)->color.degamma_lut_size);
|
|
|
|
intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
|
|
I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
|
|
POSTING_READ(GAMMA_MODE(pipe));
|
|
|
|
/*
|
|
* Reset the index, otherwise it prevents the legacy palette to be
|
|
* written properly.
|
|
*/
|
|
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
|
|
}
|
|
|
|
static void glk_load_degamma_lut(struct drm_crtc_state *state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
|
|
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
|
|
const uint32_t lut_size = 33;
|
|
uint32_t i;
|
|
|
|
/*
|
|
* When setting the auto-increment bit, the hardware seems to
|
|
* ignore the index bits, so we need to reset it to index 0
|
|
* separately.
|
|
*/
|
|
I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
|
|
I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
|
|
|
|
/*
|
|
* FIXME: The pipe degamma table in geminilake doesn't support
|
|
* different values per channel, so this just loads a linear table.
|
|
*/
|
|
for (i = 0; i < lut_size; i++) {
|
|
uint32_t v = (i * (1 << 16)) / (lut_size - 1);
|
|
|
|
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
|
|
}
|
|
|
|
/* Clamp values > 1.0. */
|
|
while (i++ < 35)
|
|
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
|
|
}
|
|
|
|
static void glk_load_luts(struct drm_crtc_state *state)
|
|
{
|
|
struct drm_crtc *crtc = state->crtc;
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
|
|
enum pipe pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
glk_load_degamma_lut(state);
|
|
|
|
if (crtc_state_is_legacy(state)) {
|
|
haswell_load_luts(state);
|
|
return;
|
|
}
|
|
|
|
bdw_load_gamma_lut(state, 0);
|
|
|
|
intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
|
|
I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
|
|
POSTING_READ(GAMMA_MODE(pipe));
|
|
}
|
|
|
|
/* Loads the palette/gamma unit for the CRTC on CherryView. */
|
|
static void cherryview_load_luts(struct drm_crtc_state *state)
|
|
{
|
|
struct drm_crtc *crtc = state->crtc;
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
enum pipe pipe = to_intel_crtc(crtc)->pipe;
|
|
struct drm_color_lut *lut;
|
|
uint32_t i, lut_size;
|
|
uint32_t word0, word1;
|
|
|
|
if (crtc_state_is_legacy(state)) {
|
|
/* Turn off degamma/gamma on CGM block. */
|
|
I915_WRITE(CGM_PIPE_MODE(pipe),
|
|
(state->ctm ? CGM_PIPE_MODE_CSC : 0));
|
|
i9xx_load_luts_internal(crtc, state->gamma_lut,
|
|
to_intel_crtc_state(state));
|
|
return;
|
|
}
|
|
|
|
if (state->degamma_lut) {
|
|
lut = (struct drm_color_lut *) state->degamma_lut->data;
|
|
lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
|
|
for (i = 0; i < lut_size; i++) {
|
|
/* Write LUT in U0.14 format. */
|
|
word0 =
|
|
(drm_color_lut_extract(lut[i].green, 14) << 16) |
|
|
drm_color_lut_extract(lut[i].blue, 14);
|
|
word1 = drm_color_lut_extract(lut[i].red, 14);
|
|
|
|
I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
|
|
I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
|
|
}
|
|
}
|
|
|
|
if (state->gamma_lut) {
|
|
lut = (struct drm_color_lut *) state->gamma_lut->data;
|
|
lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
|
|
for (i = 0; i < lut_size; i++) {
|
|
/* Write LUT in U0.10 format. */
|
|
word0 =
|
|
(drm_color_lut_extract(lut[i].green, 10) << 16) |
|
|
drm_color_lut_extract(lut[i].blue, 10);
|
|
word1 = drm_color_lut_extract(lut[i].red, 10);
|
|
|
|
I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
|
|
I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
|
|
}
|
|
}
|
|
|
|
I915_WRITE(CGM_PIPE_MODE(pipe),
|
|
(state->ctm ? CGM_PIPE_MODE_CSC : 0) |
|
|
(state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
|
|
(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
|
|
|
|
/*
|
|
* Also program a linear LUT in the legacy block (behind the
|
|
* CGM block).
|
|
*/
|
|
i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
|
|
}
|
|
|
|
void intel_color_load_luts(struct drm_crtc_state *crtc_state)
|
|
{
|
|
struct drm_device *dev = crtc_state->crtc->dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
dev_priv->display.load_luts(crtc_state);
|
|
}
|
|
|
|
int intel_color_check(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
size_t gamma_length, degamma_length;
|
|
|
|
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
|
|
sizeof(struct drm_color_lut);
|
|
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
|
|
sizeof(struct drm_color_lut);
|
|
|
|
/*
|
|
* We allow both degamma & gamma luts at the right size or
|
|
* NULL.
|
|
*/
|
|
if ((!crtc_state->degamma_lut ||
|
|
crtc_state->degamma_lut->length == degamma_length) &&
|
|
(!crtc_state->gamma_lut ||
|
|
crtc_state->gamma_lut->length == gamma_length))
|
|
return 0;
|
|
|
|
/*
|
|
* We also allow no degamma lut and a gamma lut at the legacy
|
|
* size (256 entries).
|
|
*/
|
|
if (!crtc_state->degamma_lut &&
|
|
crtc_state->gamma_lut &&
|
|
crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH)
|
|
return 0;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
void intel_color_init(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
|
|
drm_mode_crtc_set_gamma_size(crtc, 256);
|
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
|
|
dev_priv->display.load_luts = cherryview_load_luts;
|
|
} else if (IS_HASWELL(dev_priv)) {
|
|
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
|
|
dev_priv->display.load_luts = haswell_load_luts;
|
|
} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
|
|
IS_BROXTON(dev_priv)) {
|
|
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
|
|
dev_priv->display.load_luts = broadwell_load_luts;
|
|
} else if (IS_GEMINILAKE(dev_priv)) {
|
|
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
|
|
dev_priv->display.load_luts = glk_load_luts;
|
|
} else {
|
|
dev_priv->display.load_luts = i9xx_load_luts;
|
|
}
|
|
|
|
/* Enable color management support when we have degamma & gamma LUTs. */
|
|
if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
|
|
INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
|
|
drm_crtc_enable_color_mgmt(crtc,
|
|
INTEL_INFO(dev_priv)->color.degamma_lut_size,
|
|
true,
|
|
INTEL_INFO(dev_priv)->color.gamma_lut_size);
|
|
}
|