234 lines
6.1 KiB
C
234 lines
6.1 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Contributors:
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* Manjunath Hadli <manjunath.hadli@ti.com>
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* Prabhakar Lad <prabhakar.lad@ti.com>
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*/
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#ifndef _DAVINCI_VPFE_DM365_IPIPEIF_H
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#define _DAVINCI_VPFE_DM365_IPIPEIF_H
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#include <linux/platform_device.h>
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#include <media/davinci/vpss.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-subdev.h>
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#include "dm365_ipipeif_user.h"
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#include "vpfe_video.h"
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/* IPIPE base specific types */
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enum ipipeif_data_shift {
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IPIPEIF_BITS15_2 = 0,
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IPIPEIF_BITS14_1 = 1,
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IPIPEIF_BITS13_0 = 2,
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IPIPEIF_BITS12_0 = 3,
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IPIPEIF_BITS11_0 = 4,
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IPIPEIF_BITS10_0 = 5,
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IPIPEIF_BITS9_0 = 6,
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};
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enum ipipeif_clkdiv {
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IPIPEIF_DIVIDE_HALF = 0,
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IPIPEIF_DIVIDE_THIRD = 1,
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IPIPEIF_DIVIDE_FOURTH = 2,
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IPIPEIF_DIVIDE_FIFTH = 3,
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IPIPEIF_DIVIDE_SIXTH = 4,
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IPIPEIF_DIVIDE_EIGHTH = 5,
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IPIPEIF_DIVIDE_SIXTEENTH = 6,
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IPIPEIF_DIVIDE_THIRTY = 7,
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};
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enum ipipeif_pack_mode {
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IPIPEIF_PACK_16_BIT = 0,
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IPIPEIF_PACK_8_BIT = 1,
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};
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enum ipipeif_5_1_pack_mode {
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IPIPEIF_5_1_PACK_16_BIT = 0,
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IPIPEIF_5_1_PACK_8_BIT = 1,
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IPIPEIF_5_1_PACK_8_BIT_A_LAW = 2,
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IPIPEIF_5_1_PACK_12_BIT = 3
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};
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enum ipipeif_input_source {
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IPIPEIF_CCDC = 0,
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IPIPEIF_SDRAM_RAW = 1,
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IPIPEIF_CCDC_DARKFM = 2,
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IPIPEIF_SDRAM_YUV = 3,
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};
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enum ipipeif_ialaw {
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IPIPEIF_ALAW_OFF = 0,
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IPIPEIF_ALAW_ON = 1,
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};
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enum ipipeif_input_src1 {
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IPIPEIF_SRC1_PARALLEL_PORT = 0,
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IPIPEIF_SRC1_SDRAM_RAW = 1,
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IPIPEIF_SRC1_ISIF_DARKFM = 2,
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IPIPEIF_SRC1_SDRAM_YUV = 3,
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};
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enum ipipeif_dfs_dir {
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IPIPEIF_PORT_MINUS_SDRAM = 0,
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IPIPEIF_SDRAM_MINUS_PORT = 1,
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};
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enum ipipeif_chroma_phase {
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IPIPEIF_CBCR_Y = 0,
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IPIPEIF_Y_CBCR = 1,
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};
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enum ipipeif_dpcm_type {
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IPIPEIF_DPCM_8BIT_10BIT = 0,
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IPIPEIF_DPCM_8BIT_12BIT = 1,
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};
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/* data shift for IPIPE 5.1 */
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enum ipipeif_5_1_data_shift {
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IPIPEIF_5_1_BITS11_0 = 0,
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IPIPEIF_5_1_BITS10_0 = 1,
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IPIPEIF_5_1_BITS9_0 = 2,
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IPIPEIF_5_1_BITS8_0 = 3,
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IPIPEIF_5_1_BITS7_0 = 4,
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IPIPEIF_5_1_BITS15_4 = 5,
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};
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#define IPIPEIF_PAD_SINK 0
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#define IPIPEIF_PAD_SOURCE 1
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#define IPIPEIF_NUM_PADS 2
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enum ipipeif_input_entity {
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IPIPEIF_INPUT_NONE = 0,
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IPIPEIF_INPUT_ISIF = 1,
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IPIPEIF_INPUT_MEMORY = 2,
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};
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enum ipipeif_output_entity {
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IPIPEIF_OUTPUT_NONE = 0,
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IPIPEIF_OUTPUT_IPIPE = 1,
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IPIPEIF_OUTPUT_RESIZER = 2,
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};
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struct vpfe_ipipeif_device {
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struct v4l2_subdev subdev;
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struct media_pad pads[IPIPEIF_NUM_PADS];
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struct v4l2_mbus_framefmt formats[IPIPEIF_NUM_PADS];
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enum ipipeif_input_entity input;
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unsigned int output;
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struct vpfe_video_device video_in;
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struct v4l2_ctrl_handler ctrls;
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void __iomem *ipipeif_base_addr;
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struct ipipeif_params config;
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int dpcm_predictor;
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int gain;
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};
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/* IPIPEIF Register Offsets from the base address */
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#define IPIPEIF_ENABLE 0x00
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#define IPIPEIF_CFG1 0x04
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#define IPIPEIF_PPLN 0x08
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#define IPIPEIF_LPFR 0x0c
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#define IPIPEIF_HNUM 0x10
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#define IPIPEIF_VNUM 0x14
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#define IPIPEIF_ADDRU 0x18
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#define IPIPEIF_ADDRL 0x1c
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#define IPIPEIF_ADOFS 0x20
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#define IPIPEIF_RSZ 0x24
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#define IPIPEIF_GAIN 0x28
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/* Below registers are available only on IPIPE 5.1 */
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#define IPIPEIF_DPCM 0x2c
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#define IPIPEIF_CFG2 0x30
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#define IPIPEIF_INIRSZ 0x34
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#define IPIPEIF_OCLIP 0x38
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#define IPIPEIF_DTUDF 0x3c
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#define IPIPEIF_CLKDIV 0x40
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#define IPIPEIF_DPC1 0x44
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#define IPIPEIF_DPC2 0x48
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#define IPIPEIF_DFSGVL 0x4c
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#define IPIPEIF_DFSGTH 0x50
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#define IPIPEIF_RSZ3A 0x54
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#define IPIPEIF_INIRSZ3A 0x58
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#define IPIPEIF_RSZ_MIN 16
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#define IPIPEIF_RSZ_MAX 112
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#define IPIPEIF_RSZ_CONST 16
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#define SETBIT(reg, bit) (reg = ((reg) | ((0x00000001)<<(bit))))
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#define RESETBIT(reg, bit) (reg = ((reg) & (~(0x00000001<<(bit)))))
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#define IPIPEIF_ADOFS_LSB_MASK 0x1ff
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#define IPIPEIF_ADOFS_LSB_SHIFT 5
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#define IPIPEIF_ADOFS_MSB_MASK 0x200
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#define IPIPEIF_ADDRU_MASK 0x7ff
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#define IPIPEIF_ADDRL_SHIFT 5
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#define IPIPEIF_ADDRL_MASK 0xffff
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#define IPIPEIF_ADDRU_SHIFT 21
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#define IPIPEIF_ADDRMSB_SHIFT 31
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#define IPIPEIF_ADDRMSB_LEFT_SHIFT 10
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/* CFG1 Masks and shifts */
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#define ONESHOT_SHIFT 0
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#define DECIM_SHIFT 1
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#define INPSRC_SHIFT 2
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#define CLKDIV_SHIFT 4
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#define AVGFILT_SHIFT 7
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#define PACK8IN_SHIFT 8
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#define IALAW_SHIFT 9
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#define CLKSEL_SHIFT 10
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#define DATASFT_SHIFT 11
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#define INPSRC1_SHIFT 14
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/* DPC2 */
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#define IPIPEIF_DPC2_EN_SHIFT 12
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#define IPIPEIF_DPC2_THR_MASK 0xfff
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/* Applicable for IPIPE 5.1 */
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#define IPIPEIF_DF_GAIN_EN_SHIFT 10
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#define IPIPEIF_DF_GAIN_MASK 0x3ff
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#define IPIPEIF_DF_GAIN_THR_MASK 0xfff
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/* DPCM */
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#define IPIPEIF_DPCM_BITS_SHIFT 2
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#define IPIPEIF_DPCM_PRED_SHIFT 1
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/* CFG2 */
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#define IPIPEIF_CFG2_HDPOL_SHIFT 1
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#define IPIPEIF_CFG2_VDPOL_SHIFT 2
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#define IPIPEIF_CFG2_YUV8_SHIFT 6
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#define IPIPEIF_CFG2_YUV16_SHIFT 3
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#define IPIPEIF_CFG2_YUV8P_SHIFT 7
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/* INIRSZ */
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#define IPIPEIF_INIRSZ_ALNSYNC_SHIFT 13
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#define IPIPEIF_INIRSZ_MASK 0x1fff
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/* CLKDIV */
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#define IPIPEIF_CLKDIV_M_SHIFT 8
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void vpfe_ipipeif_enable(struct vpfe_device *vpfe_dev);
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void vpfe_ipipeif_ss_buffer_isr(struct vpfe_ipipeif_device *ipipeif);
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int vpfe_ipipeif_decimation_enabled(struct vpfe_device *vpfe_dev);
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int vpfe_ipipeif_get_rsz(struct vpfe_device *vpfe_dev);
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void vpfe_ipipeif_cleanup(struct vpfe_ipipeif_device *ipipeif,
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struct platform_device *pdev);
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int vpfe_ipipeif_init(struct vpfe_ipipeif_device *ipipeif,
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struct platform_device *pdev);
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int vpfe_ipipeif_register_entities(struct vpfe_ipipeif_device *ipipeif,
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struct v4l2_device *vdev);
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void vpfe_ipipeif_unregister_entities(struct vpfe_ipipeif_device *ipipeif);
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#endif /* _DAVINCI_VPFE_DM365_IPIPEIF_H */
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