713 lines
23 KiB
C
713 lines
23 KiB
C
/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "ssi_config.h"
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <crypto/ctr.h>
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#ifdef FLUSH_CACHE_ALL
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#include <asm/cacheflush.h>
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#endif
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#include <linux/pm_runtime.h>
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#include "ssi_driver.h"
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#include "ssi_buffer_mgr.h"
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#include "ssi_request_mgr.h"
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#include "ssi_sysfs.h"
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#include "ssi_ivgen.h"
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#include "ssi_pm.h"
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#include "ssi_fips.h"
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#include "ssi_fips_local.h"
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#define SSI_MAX_POLL_ITER 10
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#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
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#ifdef CC_CYCLE_COUNT
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#define MONITOR_CNTR_BIT 0
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/**
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* Monitor descriptor.
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* Used to measure CC performance.
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*/
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#define INIT_CC_MONITOR_DESC(desc_p) \
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do { \
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HW_DESC_INIT(desc_p); \
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HW_DESC_SET_DIN_MONITOR_CNTR(desc_p); \
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} while (0)
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/**
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* Try adding monitor descriptor BEFORE enqueuing sequence.
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*/
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#define CC_CYCLE_DESC_HEAD(cc_base_addr, desc_p, lock_p, is_monitored_p) \
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do { \
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if (!test_and_set_bit(MONITOR_CNTR_BIT, (lock_p))) { \
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enqueue_seq((cc_base_addr), (desc_p), 1); \
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*(is_monitored_p) = true; \
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} else { \
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*(is_monitored_p) = false; \
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} \
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} while (0)
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/**
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* If CC_CYCLE_DESC_HEAD was successfully added:
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* 1. Add memory barrier descriptor to ensure last AXI transaction.
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* 2. Add monitor descriptor to sequence tail AFTER enqueuing sequence.
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*/
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#define CC_CYCLE_DESC_TAIL(cc_base_addr, desc_p, is_monitored) \
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do { \
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if ((is_monitored) == true) { \
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HwDesc_s barrier_desc; \
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HW_DESC_INIT(&barrier_desc); \
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HW_DESC_SET_DIN_NO_DMA(&barrier_desc, 0, 0xfffff0); \
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HW_DESC_SET_DOUT_NO_DMA(&barrier_desc, 0, 0, 1); \
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enqueue_seq((cc_base_addr), &barrier_desc, 1); \
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enqueue_seq((cc_base_addr), (desc_p), 1); \
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} \
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} while (0)
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/**
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* Try reading CC monitor counter value upon sequence complete.
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* Can only succeed if the lock_p is taken by the owner of the given request.
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*/
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#define END_CC_MONITOR_COUNT(cc_base_addr, stat_op_type, stat_phase, monitor_null_cycles, lock_p, is_monitored) \
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do { \
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uint32_t elapsed_cycles; \
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if ((is_monitored) == true) { \
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elapsed_cycles = READ_REGISTER((cc_base_addr) + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR)); \
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clear_bit(MONITOR_CNTR_BIT, (lock_p)); \
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if (elapsed_cycles > 0) \
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update_cc_stat(stat_op_type, stat_phase, (elapsed_cycles - monitor_null_cycles)); \
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} \
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} while (0)
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#else /*CC_CYCLE_COUNT*/
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#define INIT_CC_MONITOR_DESC(desc_p) do { } while (0)
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#define CC_CYCLE_DESC_HEAD(cc_base_addr, desc_p, lock_p, is_monitored_p) do { } while (0)
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#define CC_CYCLE_DESC_TAIL(cc_base_addr, desc_p, is_monitored) do { } while (0)
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#define END_CC_MONITOR_COUNT(cc_base_addr, stat_op_type, stat_phase, monitor_null_cycles, lock_p, is_monitored) do { } while (0)
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#endif /*CC_CYCLE_COUNT*/
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struct ssi_request_mgr_handle {
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/* Request manager resources */
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unsigned int hw_queue_size; /* HW capability */
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unsigned int min_free_hw_slots;
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unsigned int max_used_sw_slots;
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struct ssi_crypto_req req_queue[MAX_REQUEST_QUEUE_SIZE];
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uint32_t req_queue_head;
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uint32_t req_queue_tail;
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uint32_t axi_completed;
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uint32_t q_free_slots;
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spinlock_t hw_lock;
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HwDesc_s compl_desc;
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uint8_t *dummy_comp_buff;
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dma_addr_t dummy_comp_buff_dma;
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HwDesc_s monitor_desc;
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volatile unsigned long monitor_lock;
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#ifdef COMP_IN_WQ
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struct workqueue_struct *workq;
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struct delayed_work compwork;
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#else
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struct tasklet_struct comptask;
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#endif
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#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
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bool is_runtime_suspended;
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#endif
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};
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static void comp_handler(unsigned long devarg);
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#ifdef COMP_IN_WQ
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static void comp_work_handler(struct work_struct *work);
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#endif
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void request_mgr_fini(struct ssi_drvdata *drvdata)
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{
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struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
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if (req_mgr_h == NULL)
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return; /* Not allocated */
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if (req_mgr_h->dummy_comp_buff_dma != 0) {
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SSI_RESTORE_DMA_ADDR_TO_48BIT(req_mgr_h->dummy_comp_buff_dma);
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dma_free_coherent(&drvdata->plat_dev->dev,
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sizeof(uint32_t), req_mgr_h->dummy_comp_buff,
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req_mgr_h->dummy_comp_buff_dma);
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}
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SSI_LOG_DEBUG("max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size -
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req_mgr_h->min_free_hw_slots) );
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SSI_LOG_DEBUG("max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots);
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#ifdef COMP_IN_WQ
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flush_workqueue(req_mgr_h->workq);
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destroy_workqueue(req_mgr_h->workq);
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#else
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/* Kill tasklet */
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tasklet_kill(&req_mgr_h->comptask);
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#endif
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memset(req_mgr_h, 0, sizeof(struct ssi_request_mgr_handle));
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kfree(req_mgr_h);
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drvdata->request_mgr_handle = NULL;
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}
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int request_mgr_init(struct ssi_drvdata *drvdata)
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{
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#ifdef CC_CYCLE_COUNT
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HwDesc_s monitor_desc[2];
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struct ssi_crypto_req monitor_req = {0};
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#endif
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struct ssi_request_mgr_handle *req_mgr_h;
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int rc = 0;
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req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle),GFP_KERNEL);
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if (req_mgr_h == NULL) {
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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drvdata->request_mgr_handle = req_mgr_h;
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spin_lock_init(&req_mgr_h->hw_lock);
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#ifdef COMP_IN_WQ
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SSI_LOG_DEBUG("Initializing completion workqueue\n");
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req_mgr_h->workq = create_singlethread_workqueue("arm_cc7x_wq");
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if (unlikely(req_mgr_h->workq == NULL)) {
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SSI_LOG_ERR("Failed creating work queue\n");
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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INIT_DELAYED_WORK(&req_mgr_h->compwork, comp_work_handler);
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#else
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SSI_LOG_DEBUG("Initializing completion tasklet\n");
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tasklet_init(&req_mgr_h->comptask, comp_handler, (unsigned long)drvdata);
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#endif
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req_mgr_h->hw_queue_size = READ_REGISTER(drvdata->cc_base +
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CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_SRAM_SIZE));
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SSI_LOG_DEBUG("hw_queue_size=0x%08X\n", req_mgr_h->hw_queue_size);
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if (req_mgr_h->hw_queue_size < MIN_HW_QUEUE_SIZE) {
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SSI_LOG_ERR("Invalid HW queue size = %u (Min. required is %u)\n",
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req_mgr_h->hw_queue_size, MIN_HW_QUEUE_SIZE);
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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req_mgr_h->min_free_hw_slots = req_mgr_h->hw_queue_size;
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req_mgr_h->max_used_sw_slots = 0;
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/* Allocate DMA word for "dummy" completion descriptor use */
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req_mgr_h->dummy_comp_buff = dma_alloc_coherent(&drvdata->plat_dev->dev,
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sizeof(uint32_t), &req_mgr_h->dummy_comp_buff_dma, GFP_KERNEL);
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if (!req_mgr_h->dummy_comp_buff) {
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SSI_LOG_ERR("Not enough memory to allocate DMA (%zu) dropped "
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"buffer\n", sizeof(uint32_t));
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rc = -ENOMEM;
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goto req_mgr_init_err;
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}
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SSI_UPDATE_DMA_ADDR_TO_48BIT(req_mgr_h->dummy_comp_buff_dma,
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sizeof(uint32_t));
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/* Init. "dummy" completion descriptor */
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HW_DESC_INIT(&req_mgr_h->compl_desc);
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HW_DESC_SET_DIN_CONST(&req_mgr_h->compl_desc, 0, sizeof(uint32_t));
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HW_DESC_SET_DOUT_DLLI(&req_mgr_h->compl_desc,
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req_mgr_h->dummy_comp_buff_dma,
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sizeof(uint32_t), NS_BIT, 1);
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HW_DESC_SET_FLOW_MODE(&req_mgr_h->compl_desc, BYPASS);
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HW_DESC_SET_QUEUE_LAST_IND(&req_mgr_h->compl_desc);
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#ifdef CC_CYCLE_COUNT
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/* For CC-HW cycle performance trace */
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INIT_CC_MONITOR_DESC(&req_mgr_h->monitor_desc);
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set_bit(MONITOR_CNTR_BIT, &req_mgr_h->monitor_lock);
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monitor_desc[0] = req_mgr_h->monitor_desc;
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monitor_desc[1] = req_mgr_h->monitor_desc;
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rc = send_request(drvdata, &monitor_req, monitor_desc, 2, 0);
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if (unlikely(rc != 0))
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goto req_mgr_init_err;
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drvdata->monitor_null_cycles = READ_REGISTER(drvdata->cc_base +
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CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR));
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SSI_LOG_ERR("Calibration time=0x%08x\n", drvdata->monitor_null_cycles);
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clear_bit(MONITOR_CNTR_BIT, &req_mgr_h->monitor_lock);
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#endif
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return 0;
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req_mgr_init_err:
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request_mgr_fini(drvdata);
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return rc;
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}
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static inline void enqueue_seq(
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void __iomem *cc_base,
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HwDesc_s seq[], unsigned int seq_len)
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{
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int i;
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for (i = 0; i < seq_len; i++) {
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writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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wmb();
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writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
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#ifdef DX_DUMP_DESCS
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SSI_LOG_DEBUG("desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
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seq[i].word[0], seq[i].word[1], seq[i].word[2], seq[i].word[3], seq[i].word[4], seq[i].word[5]);
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#endif
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}
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}
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/*!
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* Completion will take place if and only if user requested completion
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* by setting "is_dout = 0" in send_request().
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*
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* \param dev
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* \param dx_compl_h The completion event to signal
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*/
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static void request_mgr_complete(struct device *dev, void *dx_compl_h, void __iomem *cc_base)
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{
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struct completion *this_compl = dx_compl_h;
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complete(this_compl);
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}
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static inline int request_mgr_queues_status_check(
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struct ssi_request_mgr_handle *req_mgr_h,
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void __iomem *cc_base,
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unsigned int total_seq_len)
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{
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unsigned long poll_queue;
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/* SW queue is checked only once as it will not
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be chaned during the poll becasue the spinlock_bh
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is held by the thread */
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if (unlikely(((req_mgr_h->req_queue_head + 1) &
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(MAX_REQUEST_QUEUE_SIZE - 1)) ==
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req_mgr_h->req_queue_tail)) {
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SSI_LOG_ERR("SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n",
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req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE);
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return -EBUSY;
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}
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if ((likely(req_mgr_h->q_free_slots >= total_seq_len)) ) {
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return 0;
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}
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/* Wait for space in HW queue. Poll constant num of iterations. */
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for (poll_queue =0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue ++) {
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req_mgr_h->q_free_slots =
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CC_HAL_READ_REGISTER(
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CC_REG_OFFSET(CRY_KERNEL,
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DSCRPTR_QUEUE_CONTENT));
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if (unlikely(req_mgr_h->q_free_slots <
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req_mgr_h->min_free_hw_slots)) {
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req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots;
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}
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if (likely (req_mgr_h->q_free_slots >= total_seq_len)) {
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/* If there is enough place return */
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return 0;
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}
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SSI_LOG_DEBUG("HW FIFO is full. q_free_slots=%d total_seq_len=%d\n",
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req_mgr_h->q_free_slots, total_seq_len);
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}
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/* No room in the HW queue try again later */
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SSI_LOG_DEBUG("HW FIFO full, timeout. req_queue_head=%d "
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"sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n",
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req_mgr_h->req_queue_head,
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MAX_REQUEST_QUEUE_SIZE,
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req_mgr_h->q_free_slots,
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total_seq_len);
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return -EAGAIN;
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}
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/*!
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* Enqueue caller request to crypto hardware.
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*
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* \param drvdata
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* \param ssi_req The request to enqueue
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* \param desc The crypto sequence
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* \param len The crypto sequence length
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* \param is_dout If "true": completion is handled by the caller
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* If "false": this function adds a dummy descriptor completion
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* and waits upon completion signal.
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*
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* \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false"
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*/
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int send_request(
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struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req,
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HwDesc_s *desc, unsigned int len, bool is_dout)
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{
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void __iomem *cc_base = drvdata->cc_base;
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struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
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unsigned int used_sw_slots;
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unsigned int iv_seq_len = 0;
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unsigned int total_seq_len = len; /*initial sequence length*/
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HwDesc_s iv_seq[SSI_IVPOOL_SEQ_LEN];
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int rc;
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unsigned int max_required_seq_len = (total_seq_len +
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((ssi_req->ivgen_dma_addr_len == 0) ? 0 :
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SSI_IVPOOL_SEQ_LEN ) +
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((is_dout == 0 )? 1 : 0));
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DECL_CYCLE_COUNT_RESOURCES;
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#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
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rc = ssi_power_mgr_runtime_get(&drvdata->plat_dev->dev);
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if (rc != 0) {
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SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n",rc);
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return rc;
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}
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#endif
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do {
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spin_lock_bh(&req_mgr_h->hw_lock);
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/* Check if there is enough place in the SW/HW queues
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in case iv gen add the max size and in case of no dout add 1
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for the internal completion descriptor */
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rc = request_mgr_queues_status_check(req_mgr_h,
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cc_base,
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max_required_seq_len);
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if (likely(rc == 0 ))
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/* There is enough place in the queue */
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break;
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/* something wrong release the spinlock*/
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spin_unlock_bh(&req_mgr_h->hw_lock);
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if (rc != -EAGAIN) {
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/* Any error other than HW queue full
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(SW queue is full) */
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#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
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ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
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#endif
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return rc;
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}
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/* HW queue is full - short sleep */
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msleep(1);
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} while (1);
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/* Additional completion descriptor is needed incase caller did not
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enabled any DLLI/MLLI DOUT bit in the given sequence */
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if (!is_dout) {
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init_completion(&ssi_req->seq_compl);
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ssi_req->user_cb = request_mgr_complete;
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ssi_req->user_arg = &(ssi_req->seq_compl);
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total_seq_len++;
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}
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if (ssi_req->ivgen_dma_addr_len > 0) {
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SSI_LOG_DEBUG("Acquire IV from pool into %d DMA addresses 0x%llX, 0x%llX, 0x%llX, IV-size=%u\n",
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ssi_req->ivgen_dma_addr_len,
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(unsigned long long)ssi_req->ivgen_dma_addr[0],
|
|
(unsigned long long)ssi_req->ivgen_dma_addr[1],
|
|
(unsigned long long)ssi_req->ivgen_dma_addr[2],
|
|
ssi_req->ivgen_size);
|
|
|
|
/* Acquire IV from pool */
|
|
rc = ssi_ivgen_getiv(drvdata, ssi_req->ivgen_dma_addr, ssi_req->ivgen_dma_addr_len,
|
|
ssi_req->ivgen_size, iv_seq, &iv_seq_len);
|
|
|
|
if (unlikely(rc != 0)) {
|
|
SSI_LOG_ERR("Failed to generate IV (rc=%d)\n", rc);
|
|
spin_unlock_bh(&req_mgr_h->hw_lock);
|
|
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
|
ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
|
|
#endif
|
|
return rc;
|
|
}
|
|
|
|
total_seq_len += iv_seq_len;
|
|
}
|
|
|
|
used_sw_slots = ((req_mgr_h->req_queue_head - req_mgr_h->req_queue_tail) & (MAX_REQUEST_QUEUE_SIZE-1));
|
|
if (unlikely(used_sw_slots > req_mgr_h->max_used_sw_slots)) {
|
|
req_mgr_h->max_used_sw_slots = used_sw_slots;
|
|
}
|
|
|
|
CC_CYCLE_DESC_HEAD(cc_base, &req_mgr_h->monitor_desc,
|
|
&req_mgr_h->monitor_lock, &ssi_req->is_monitored_p);
|
|
|
|
/* Enqueue request - must be locked with HW lock*/
|
|
req_mgr_h->req_queue[req_mgr_h->req_queue_head] = *ssi_req;
|
|
START_CYCLE_COUNT_AT(req_mgr_h->req_queue[req_mgr_h->req_queue_head].submit_cycle);
|
|
req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
|
|
/* TODO: Use circ_buf.h ? */
|
|
|
|
SSI_LOG_DEBUG("Enqueue request head=%u\n", req_mgr_h->req_queue_head);
|
|
|
|
#ifdef FLUSH_CACHE_ALL
|
|
flush_cache_all();
|
|
#endif
|
|
|
|
/* STAT_PHASE_4: Push sequence */
|
|
START_CYCLE_COUNT();
|
|
enqueue_seq(cc_base, iv_seq, iv_seq_len);
|
|
enqueue_seq(cc_base, desc, len);
|
|
enqueue_seq(cc_base, &req_mgr_h->compl_desc, (is_dout ? 0 : 1));
|
|
END_CYCLE_COUNT(ssi_req->op_type, STAT_PHASE_4);
|
|
|
|
CC_CYCLE_DESC_TAIL(cc_base, &req_mgr_h->monitor_desc, ssi_req->is_monitored_p);
|
|
|
|
if (unlikely(req_mgr_h->q_free_slots < total_seq_len)) {
|
|
/*This means that there was a problem with the resume*/
|
|
BUG();
|
|
}
|
|
/* Update the free slots in HW queue */
|
|
req_mgr_h->q_free_slots -= total_seq_len;
|
|
|
|
spin_unlock_bh(&req_mgr_h->hw_lock);
|
|
|
|
if (!is_dout) {
|
|
/* Wait upon sequence completion.
|
|
* Return "0" -Operation done successfully. */
|
|
return wait_for_completion_interruptible(&ssi_req->seq_compl);
|
|
} else {
|
|
/* Operation still in process */
|
|
return -EINPROGRESS;
|
|
}
|
|
}
|
|
|
|
|
|
/*!
|
|
* Enqueue caller request to crypto hardware during init process.
|
|
* assume this function is not called in middle of a flow,
|
|
* since we set QUEUE_LAST_IND flag in the last descriptor.
|
|
*
|
|
* \param drvdata
|
|
* \param desc The crypto sequence
|
|
* \param len The crypto sequence length
|
|
*
|
|
* \return int Returns "0" upon success
|
|
*/
|
|
int send_request_init(
|
|
struct ssi_drvdata *drvdata, HwDesc_s *desc, unsigned int len)
|
|
{
|
|
void __iomem *cc_base = drvdata->cc_base;
|
|
struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
|
|
unsigned int total_seq_len = len; /*initial sequence length*/
|
|
int rc = 0;
|
|
|
|
/* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */
|
|
rc = request_mgr_queues_status_check(req_mgr_h, cc_base, total_seq_len);
|
|
if (unlikely(rc != 0 )) {
|
|
return rc;
|
|
}
|
|
HW_DESC_SET_QUEUE_LAST_IND(&desc[len-1]);
|
|
|
|
enqueue_seq(cc_base, desc, len);
|
|
|
|
/* Update the free slots in HW queue */
|
|
req_mgr_h->q_free_slots = CC_HAL_READ_REGISTER(
|
|
CC_REG_OFFSET(CRY_KERNEL,
|
|
DSCRPTR_QUEUE_CONTENT));
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void complete_request(struct ssi_drvdata *drvdata)
|
|
{
|
|
struct ssi_request_mgr_handle *request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
#ifdef COMP_IN_WQ
|
|
queue_delayed_work(request_mgr_handle->workq, &request_mgr_handle->compwork, 0);
|
|
#else
|
|
tasklet_schedule(&request_mgr_handle->comptask);
|
|
#endif
|
|
}
|
|
|
|
#ifdef COMP_IN_WQ
|
|
static void comp_work_handler(struct work_struct *work)
|
|
{
|
|
struct ssi_drvdata *drvdata =
|
|
container_of(work, struct ssi_drvdata, compwork.work);
|
|
|
|
comp_handler((unsigned long)drvdata);
|
|
}
|
|
#endif
|
|
|
|
static void proc_completions(struct ssi_drvdata *drvdata)
|
|
{
|
|
struct ssi_crypto_req *ssi_req;
|
|
struct platform_device *plat_dev = drvdata->plat_dev;
|
|
struct ssi_request_mgr_handle * request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
|
int rc = 0;
|
|
#endif
|
|
DECL_CYCLE_COUNT_RESOURCES;
|
|
|
|
while(request_mgr_handle->axi_completed) {
|
|
request_mgr_handle->axi_completed--;
|
|
|
|
/* Dequeue request */
|
|
if (unlikely(request_mgr_handle->req_queue_head == request_mgr_handle->req_queue_tail)) {
|
|
SSI_LOG_ERR("Request queue is empty req_queue_head==req_queue_tail==%u\n", request_mgr_handle->req_queue_head);
|
|
BUG();
|
|
}
|
|
|
|
ssi_req = &request_mgr_handle->req_queue[request_mgr_handle->req_queue_tail];
|
|
END_CYCLE_COUNT_AT(ssi_req->submit_cycle, ssi_req->op_type, STAT_PHASE_5); /* Seq. Comp. */
|
|
END_CC_MONITOR_COUNT(drvdata->cc_base, ssi_req->op_type, STAT_PHASE_6,
|
|
drvdata->monitor_null_cycles, &request_mgr_handle->monitor_lock, ssi_req->is_monitored_p);
|
|
|
|
#ifdef FLUSH_CACHE_ALL
|
|
flush_cache_all();
|
|
#endif
|
|
|
|
#ifdef COMPLETION_DELAY
|
|
/* Delay */
|
|
{
|
|
uint32_t axi_err;
|
|
int i;
|
|
SSI_LOG_INFO("Delay\n");
|
|
for (i=0;i<1000000;i++) {
|
|
axi_err = READ_REGISTER(drvdata->cc_base + CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR));
|
|
}
|
|
}
|
|
#endif /* COMPLETION_DELAY */
|
|
|
|
if (likely(ssi_req->user_cb != NULL)) {
|
|
START_CYCLE_COUNT();
|
|
ssi_req->user_cb(&plat_dev->dev, ssi_req->user_arg, drvdata->cc_base);
|
|
END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_3);
|
|
}
|
|
request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
|
|
SSI_LOG_DEBUG("Dequeue request tail=%u\n", request_mgr_handle->req_queue_tail);
|
|
SSI_LOG_DEBUG("Request completed. axi_completed=%d\n", request_mgr_handle->axi_completed);
|
|
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
|
rc = ssi_power_mgr_runtime_put_suspend(&plat_dev->dev);
|
|
if (rc != 0) {
|
|
SSI_LOG_ERR("Failed to set runtime suspension %d\n",rc);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/* Deferred service handler, run as interrupt-fired tasklet */
|
|
static void comp_handler(unsigned long devarg)
|
|
{
|
|
struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg;
|
|
void __iomem *cc_base = drvdata->cc_base;
|
|
struct ssi_request_mgr_handle * request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
uint32_t irq;
|
|
|
|
DECL_CYCLE_COUNT_RESOURCES;
|
|
|
|
START_CYCLE_COUNT();
|
|
|
|
irq = (drvdata->irq & SSI_COMP_IRQ_MASK);
|
|
|
|
if (irq & SSI_COMP_IRQ_MASK) {
|
|
/* To avoid the interrupt from firing as we unmask it, we clear it now */
|
|
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
|
|
|
|
/* Avoid race with above clear: Test completion counter once more */
|
|
request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
|
|
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
|
|
|
|
/* ISR-to-Tasklet latency */
|
|
if (request_mgr_handle->axi_completed) {
|
|
/* Only if actually reflects ISR-to-completion-handling latency, i.e.,
|
|
not duplicate as a result of interrupt after AXIM_MON_ERR clear, before end of loop */
|
|
END_CYCLE_COUNT_AT(drvdata->isr_exit_cycles, STAT_OP_TYPE_GENERIC, STAT_PHASE_1);
|
|
}
|
|
|
|
while (request_mgr_handle->axi_completed) {
|
|
do {
|
|
proc_completions(drvdata);
|
|
/* At this point (after proc_completions()), request_mgr_handle->axi_completed is always 0.
|
|
The following assignment was changed to = (previously was +=) to conform KW restrictions. */
|
|
request_mgr_handle->axi_completed = CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
|
|
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
|
|
} while (request_mgr_handle->axi_completed > 0);
|
|
|
|
/* To avoid the interrupt from firing as we unmask it, we clear it now */
|
|
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
|
|
|
|
/* Avoid race with above clear: Test completion counter once more */
|
|
request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
|
|
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
|
|
}
|
|
|
|
}
|
|
/* after verifing that there is nothing to do, Unmask AXI completion interrupt */
|
|
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
|
|
CC_HAL_READ_REGISTER(
|
|
CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq);
|
|
END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_2);
|
|
}
|
|
|
|
/*
|
|
resume the queue configuration - no need to take the lock as this happens inside
|
|
the spin lock protection
|
|
*/
|
|
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
|
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
|
|
{
|
|
struct ssi_request_mgr_handle * request_mgr_handle = drvdata->request_mgr_handle;
|
|
|
|
spin_lock_bh(&request_mgr_handle->hw_lock);
|
|
request_mgr_handle->is_runtime_suspended = false;
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
|
|
return 0 ;
|
|
}
|
|
|
|
/*
|
|
suspend the queue configuration. Since it is used for the runtime suspend
|
|
only verify that the queue can be suspended.
|
|
*/
|
|
int ssi_request_mgr_runtime_suspend_queue(struct ssi_drvdata *drvdata)
|
|
{
|
|
struct ssi_request_mgr_handle * request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
/* lock the send_request */
|
|
spin_lock_bh(&request_mgr_handle->hw_lock);
|
|
if (request_mgr_handle->req_queue_head !=
|
|
request_mgr_handle->req_queue_tail) {
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
return -EBUSY;
|
|
}
|
|
request_mgr_handle->is_runtime_suspended = true;
|
|
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool ssi_request_mgr_is_queue_runtime_suspend(struct ssi_drvdata *drvdata)
|
|
{
|
|
struct ssi_request_mgr_handle * request_mgr_handle =
|
|
drvdata->request_mgr_handle;
|
|
|
|
return request_mgr_handle->is_runtime_suspended;
|
|
}
|
|
|
|
#endif
|
|
|