194 lines
6 KiB
Plaintext
194 lines
6 KiB
Plaintext
--- scripts/dtc/include-prefixes/arm64/mediatek/mt8173.dtsi 2017-08-30 04:32:30.000000000 -0400
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+++ scripts/dtc/include-prefixes/arm64/mediatek/mt8173.dtsi 2017-09-03 16:56:17.000000000 -0400
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@@ -731,8 +731,9 @@
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<0 0x11280700 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
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- phys = <&phy_port0 PHY_TYPE_USB3>,
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- <&phy_port1 PHY_TYPE_USB2>;
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+ phys = <&u2port0 PHY_TYPE_USB2>,
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+ <&u3port0 PHY_TYPE_USB3>,
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+ <&u2port1 PHY_TYPE_USB2>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
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clocks = <&topckgen CLK_TOP_USB30_SEL>,
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<&clk26m>,
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@@ -763,21 +764,31 @@
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u3phy: usb-phy@11290000 {
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compatible = "mediatek,mt8173-u3phy";
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reg = <0 0x11290000 0 0x800>;
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- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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- clock-names = "u3phya_ref";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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- phy_port0: port@11290800 {
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- reg = <0 0x11290800 0 0x800>;
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+ u2port0: usb-phy@11290800 {
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+ reg = <0 0x11290800 0 0x100>;
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+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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+ clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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- phy_port1: port@11291000 {
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- reg = <0 0x11291000 0 0x800>;
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+ u3port0: usb-phy@11290900 {
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+ reg = <0 0x11290900 0 0x700>;
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+ clocks = <&clk26m>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+
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+ u2port1: usb-phy@11291000 {
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+ reg = <0 0x11291000 0 0x100>;
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+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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+ clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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@@ -792,80 +803,74 @@
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#clock-cells = <1>;
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};
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- mdp {
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- compatible = "mediatek,mt8173-mdp";
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- #address-cells = <2>;
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- #size-cells = <2>;
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- ranges;
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+ mdp_rdma0: rdma@14001000 {
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+ compatible = "mediatek,mt8173-mdp-rdma",
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+ "mediatek,mt8173-mdp";
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+ reg = <0 0x14001000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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+ <&mmsys CLK_MM_MUTEX_32K>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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+ mediatek,larb = <&larb0>;
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mediatek,vpu = <&vpu>;
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+ };
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- mdp_rdma0: rdma@14001000 {
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- compatible = "mediatek,mt8173-mdp-rdma";
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- reg = <0 0x14001000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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- <&mmsys CLK_MM_MUTEX_32K>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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- mediatek,larb = <&larb0>;
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- };
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-
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- mdp_rdma1: rdma@14002000 {
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- compatible = "mediatek,mt8173-mdp-rdma";
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- reg = <0 0x14002000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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- <&mmsys CLK_MM_MUTEX_32K>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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- mediatek,larb = <&larb4>;
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- };
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+ mdp_rdma1: rdma@14002000 {
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+ compatible = "mediatek,mt8173-mdp-rdma";
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+ reg = <0 0x14002000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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+ <&mmsys CLK_MM_MUTEX_32K>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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+ mediatek,larb = <&larb4>;
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+ };
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- mdp_rsz0: rsz@14003000 {
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- compatible = "mediatek,mt8173-mdp-rsz";
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- reg = <0 0x14003000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- };
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+ mdp_rsz0: rsz@14003000 {
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+ compatible = "mediatek,mt8173-mdp-rsz";
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+ reg = <0 0x14003000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ };
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- mdp_rsz1: rsz@14004000 {
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- compatible = "mediatek,mt8173-mdp-rsz";
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- reg = <0 0x14004000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- };
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+ mdp_rsz1: rsz@14004000 {
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+ compatible = "mediatek,mt8173-mdp-rsz";
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+ reg = <0 0x14004000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ };
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- mdp_rsz2: rsz@14005000 {
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- compatible = "mediatek,mt8173-mdp-rsz";
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- reg = <0 0x14005000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- };
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+ mdp_rsz2: rsz@14005000 {
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+ compatible = "mediatek,mt8173-mdp-rsz";
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+ reg = <0 0x14005000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ };
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- mdp_wdma0: wdma@14006000 {
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- compatible = "mediatek,mt8173-mdp-wdma";
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- reg = <0 0x14006000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_WDMA>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- iommus = <&iommu M4U_PORT_MDP_WDMA>;
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- mediatek,larb = <&larb0>;
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- };
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+ mdp_wdma0: wdma@14006000 {
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+ compatible = "mediatek,mt8173-mdp-wdma";
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+ reg = <0 0x14006000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
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+ mediatek,larb = <&larb0>;
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+ };
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- mdp_wrot0: wrot@14007000 {
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- compatible = "mediatek,mt8173-mdp-wrot";
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- reg = <0 0x14007000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_WROT0>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- iommus = <&iommu M4U_PORT_MDP_WROT0>;
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- mediatek,larb = <&larb0>;
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- };
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+ mdp_wrot0: wrot@14007000 {
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+ compatible = "mediatek,mt8173-mdp-wrot";
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+ reg = <0 0x14007000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
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+ mediatek,larb = <&larb0>;
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+ };
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- mdp_wrot1: wrot@14008000 {
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- compatible = "mediatek,mt8173-mdp-wrot";
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- reg = <0 0x14008000 0 0x1000>;
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- clocks = <&mmsys CLK_MM_MDP_WROT1>;
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- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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- iommus = <&iommu M4U_PORT_MDP_WROT1>;
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- mediatek,larb = <&larb4>;
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- };
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+ mdp_wrot1: wrot@14008000 {
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+ compatible = "mediatek,mt8173-mdp-wrot";
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+ reg = <0 0x14008000 0 0x1000>;
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+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
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+ mediatek,larb = <&larb4>;
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};
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ovl0: ovl@1400c000 {
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