560 lines
15 KiB
C
560 lines
15 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Contributors:
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* Manjunath Hadli <manjunath.hadli@ti.com>
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* Prabhakar Lad <prabhakar.lad@ti.com>
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*/
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#ifndef _DAVINCI_VPFE_DM365_IPIPE_HW_H
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#define _DAVINCI_VPFE_DM365_IPIPE_HW_H
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#include "vpfe_mc_capture.h"
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#define SET_LOW_ADDR 0x0000ffff
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#define SET_HIGH_ADDR 0xffff0000
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/* Below are the internal tables */
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#define DPC_TB0_START_ADDR 0x8000
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#define DPC_TB1_START_ADDR 0x8400
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#define GAMMA_R_START_ADDR 0xa800
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#define GAMMA_G_START_ADDR 0xb000
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#define GAMMA_B_START_ADDR 0xb800
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/* RAM table addresses for edge enhancement correction*/
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#define YEE_TB_START_ADDR 0x8800
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/* RAM table address for GBC LUT */
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#define GBCE_TB_START_ADDR 0x9000
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/* RAM table for 3D NF LUT */
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#define D3L_TB0_START_ADDR 0x9800
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#define D3L_TB1_START_ADDR 0x9c00
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#define D3L_TB2_START_ADDR 0xa000
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#define D3L_TB3_START_ADDR 0xa400
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/* IPIPE Register Offsets from the base address */
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#define IPIPE_SRC_EN 0x0000
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#define IPIPE_SRC_MODE 0x0004
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#define IPIPE_SRC_FMT 0x0008
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#define IPIPE_SRC_COL 0x000c
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#define IPIPE_SRC_VPS 0x0010
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#define IPIPE_SRC_VSZ 0x0014
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#define IPIPE_SRC_HPS 0x0018
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#define IPIPE_SRC_HSZ 0x001c
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#define IPIPE_SEL_SBU 0x0020
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#define IPIPE_DMA_STA 0x0024
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#define IPIPE_GCK_MMR 0x0028
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#define IPIPE_GCK_PIX 0x002c
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#define IPIPE_RESERVED0 0x0030
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/* Defect Correction */
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#define DPC_LUT_EN 0x0034
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#define DPC_LUT_SEL 0x0038
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#define DPC_LUT_ADR 0x003c
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#define DPC_LUT_SIZ 0x0040
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#define DPC_OTF_EN 0x0044
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#define DPC_OTF_TYP 0x0048
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#define DPC_OTF_2D_THR_R 0x004c
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#define DPC_OTF_2D_THR_GR 0x0050
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#define DPC_OTF_2D_THR_GB 0x0054
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#define DPC_OTF_2D_THR_B 0x0058
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#define DPC_OTF_2C_THR_R 0x005c
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#define DPC_OTF_2C_THR_GR 0x0060
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#define DPC_OTF_2C_THR_GB 0x0064
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#define DPC_OTF_2C_THR_B 0x0068
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#define DPC_OTF_3_SHF 0x006c
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#define DPC_OTF_3D_THR 0x0070
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#define DPC_OTF_3D_SLP 0x0074
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#define DPC_OTF_3D_MIN 0x0078
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#define DPC_OTF_3D_MAX 0x007c
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#define DPC_OTF_3C_THR 0x0080
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#define DPC_OTF_3C_SLP 0x0084
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#define DPC_OTF_3C_MIN 0x0088
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#define DPC_OTF_3C_MAX 0x008c
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/* Lense Shading Correction */
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#define LSC_VOFT 0x90
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#define LSC_VA2 0x94
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#define LSC_VA1 0x98
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#define LSC_VS 0x9c
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#define LSC_HOFT 0xa0
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#define LSC_HA2 0xa4
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#define LSC_HA1 0xa8
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#define LSC_HS 0xac
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#define LSC_GAIN_R 0xb0
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#define LSC_GAIN_GR 0xb4
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#define LSC_GAIN_GB 0xb8
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#define LSC_GAIN_B 0xbc
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#define LSC_OFT_R 0xc0
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#define LSC_OFT_GR 0xc4
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#define LSC_OFT_GB 0xc8
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#define LSC_OFT_B 0xcc
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#define LSC_SHF 0xd0
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#define LSC_MAX 0xd4
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/* Noise Filter 1. Ofsets from start address given */
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#define D2F_1ST 0xd8
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#define D2F_EN 0x0
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#define D2F_TYP 0x4
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#define D2F_THR 0x8
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#define D2F_STR 0x28
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#define D2F_SPR 0x48
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#define D2F_EDG_MIN 0x68
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#define D2F_EDG_MAX 0x6c
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/* Noise Filter 2 */
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#define D2F_2ND 0x148
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/* GIC */
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#define GIC_EN 0x1b8
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#define GIC_TYP 0x1bc
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#define GIC_GAN 0x1c0
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#define GIC_NFGAN 0x1c4
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#define GIC_THR 0x1c8
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#define GIC_SLP 0x1cc
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/* White Balance */
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#define WB2_OFT_R 0x1d0
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#define WB2_OFT_GR 0x1d4
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#define WB2_OFT_GB 0x1d8
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#define WB2_OFT_B 0x1dc
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#define WB2_WGN_R 0x1e0
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#define WB2_WGN_GR 0x1e4
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#define WB2_WGN_GB 0x1e8
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#define WB2_WGN_B 0x1ec
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/* CFA interpolation */
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#define CFA_MODE 0x1f0
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#define CFA_2DIR_HPF_THR 0x1f4
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#define CFA_2DIR_HPF_SLP 0x1f8
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#define CFA_2DIR_MIX_THR 0x1fc
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#define CFA_2DIR_MIX_SLP 0x200
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#define CFA_2DIR_DIR_THR 0x204
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#define CFA_2DIR_DIR_SLP 0x208
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#define CFA_2DIR_NDWT 0x20c
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#define CFA_MONO_HUE_FRA 0x210
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#define CFA_MONO_EDG_THR 0x214
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#define CFA_MONO_THR_MIN 0x218
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#define CFA_MONO_THR_SLP 0x21c
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#define CFA_MONO_SLP_MIN 0x220
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#define CFA_MONO_SLP_SLP 0x224
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#define CFA_MONO_LPWT 0x228
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/* RGB to RGB conversiona - 1st */
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#define RGB1_MUL_BASE 0x22c
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/* Offsets from base */
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#define RGB_MUL_RR 0x0
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#define RGB_MUL_GR 0x4
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#define RGB_MUL_BR 0x8
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#define RGB_MUL_RG 0xc
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#define RGB_MUL_GG 0x10
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#define RGB_MUL_BG 0x14
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#define RGB_MUL_RB 0x18
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#define RGB_MUL_GB 0x1c
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#define RGB_MUL_BB 0x20
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#define RGB_OFT_OR 0x24
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#define RGB_OFT_OG 0x28
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#define RGB_OFT_OB 0x2c
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/* Gamma */
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#define GMM_CFG 0x25c
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/* RGB to RGB conversiona - 2nd */
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#define RGB2_MUL_BASE 0x260
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/* 3D LUT */
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#define D3LUT_EN 0x290
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/* RGB to YUV(YCbCr) conversion */
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#define YUV_ADJ 0x294
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#define YUV_MUL_RY 0x298
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#define YUV_MUL_GY 0x29c
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#define YUV_MUL_BY 0x2a0
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#define YUV_MUL_RCB 0x2a4
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#define YUV_MUL_GCB 0x2a8
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#define YUV_MUL_BCB 0x2ac
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#define YUV_MUL_RCR 0x2b0
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#define YUV_MUL_GCR 0x2b4
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#define YUV_MUL_BCR 0x2b8
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#define YUV_OFT_Y 0x2bc
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#define YUV_OFT_CB 0x2c0
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#define YUV_OFT_CR 0x2c4
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#define YUV_PHS 0x2c8
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/* Global Brightness and Contrast */
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#define GBCE_EN 0x2cc
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#define GBCE_TYP 0x2d0
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/* Edge Enhancer */
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#define YEE_EN 0x2d4
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#define YEE_TYP 0x2d8
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#define YEE_SHF 0x2dc
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#define YEE_MUL_00 0x2e0
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#define YEE_MUL_01 0x2e4
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#define YEE_MUL_02 0x2e8
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#define YEE_MUL_10 0x2ec
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#define YEE_MUL_11 0x2f0
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#define YEE_MUL_12 0x2f4
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#define YEE_MUL_20 0x2f8
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#define YEE_MUL_21 0x2fc
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#define YEE_MUL_22 0x300
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#define YEE_THR 0x304
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#define YEE_E_GAN 0x308
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#define YEE_E_THR1 0x30c
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#define YEE_E_THR2 0x310
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#define YEE_G_GAN 0x314
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#define YEE_G_OFT 0x318
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/* Chroma Artifact Reduction */
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#define CAR_EN 0x31c
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#define CAR_TYP 0x320
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#define CAR_SW 0x324
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#define CAR_HPF_TYP 0x328
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#define CAR_HPF_SHF 0x32c
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#define CAR_HPF_THR 0x330
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#define CAR_GN1_GAN 0x334
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#define CAR_GN1_SHF 0x338
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#define CAR_GN1_MIN 0x33c
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#define CAR_GN2_GAN 0x340
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#define CAR_GN2_SHF 0x344
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#define CAR_GN2_MIN 0x348
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/* Chroma Gain Suppression */
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#define CGS_EN 0x34c
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#define CGS_GN1_L_THR 0x350
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#define CGS_GN1_L_GAN 0x354
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#define CGS_GN1_L_SHF 0x358
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#define CGS_GN1_L_MIN 0x35c
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#define CGS_GN1_H_THR 0x360
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#define CGS_GN1_H_GAN 0x364
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#define CGS_GN1_H_SHF 0x368
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#define CGS_GN1_H_MIN 0x36c
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#define CGS_GN2_L_THR 0x370
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#define CGS_GN2_L_GAN 0x374
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#define CGS_GN2_L_SHF 0x378
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#define CGS_GN2_L_MIN 0x37c
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/* Resizer */
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#define RSZ_SRC_EN 0x0
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#define RSZ_SRC_MODE 0x4
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#define RSZ_SRC_FMT0 0x8
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#define RSZ_SRC_FMT1 0xc
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#define RSZ_SRC_VPS 0x10
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#define RSZ_SRC_VSZ 0x14
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#define RSZ_SRC_HPS 0x18
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#define RSZ_SRC_HSZ 0x1c
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#define RSZ_DMA_RZA 0x20
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#define RSZ_DMA_RZB 0x24
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#define RSZ_DMA_STA 0x28
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#define RSZ_GCK_MMR 0x2c
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#define RSZ_RESERVED0 0x30
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#define RSZ_GCK_SDR 0x34
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#define RSZ_IRQ_RZA 0x38
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#define RSZ_IRQ_RZB 0x3c
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#define RSZ_YUV_Y_MIN 0x40
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#define RSZ_YUV_Y_MAX 0x44
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#define RSZ_YUV_C_MIN 0x48
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#define RSZ_YUV_C_MAX 0x4c
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#define RSZ_YUV_PHS 0x50
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#define RSZ_SEQ 0x54
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/* Resizer Rescale Parameters */
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#define RSZ_EN_A 0x58
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#define RSZ_EN_B 0xe8
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/*
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* offset of the registers to be added with base register of
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* either RSZ0 or RSZ1
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*/
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#define RSZ_MODE 0x4
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#define RSZ_420 0x8
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#define RSZ_I_VPS 0xc
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#define RSZ_I_HPS 0x10
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#define RSZ_O_VSZ 0x14
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#define RSZ_O_HSZ 0x18
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#define RSZ_V_PHS_Y 0x1c
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#define RSZ_V_PHS_C 0x20
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#define RSZ_V_DIF 0x24
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#define RSZ_V_TYP 0x28
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#define RSZ_V_LPF 0x2c
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#define RSZ_H_PHS 0x30
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#define RSZ_H_PHS_ADJ 0x34
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#define RSZ_H_DIF 0x38
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#define RSZ_H_TYP 0x3c
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#define RSZ_H_LPF 0x40
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#define RSZ_DWN_EN 0x44
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#define RSZ_DWN_AV 0x48
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/* Resizer RGB Conversion Parameters */
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#define RSZ_RGB_EN 0x4c
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#define RSZ_RGB_TYP 0x50
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#define RSZ_RGB_BLD 0x54
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/* Resizer External Memory Parameters */
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#define RSZ_SDR_Y_BAD_H 0x58
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#define RSZ_SDR_Y_BAD_L 0x5c
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#define RSZ_SDR_Y_SAD_H 0x60
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#define RSZ_SDR_Y_SAD_L 0x64
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#define RSZ_SDR_Y_OFT 0x68
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#define RSZ_SDR_Y_PTR_S 0x6c
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#define RSZ_SDR_Y_PTR_E 0x70
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#define RSZ_SDR_C_BAD_H 0x74
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#define RSZ_SDR_C_BAD_L 0x78
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#define RSZ_SDR_C_SAD_H 0x7c
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#define RSZ_SDR_C_SAD_L 0x80
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#define RSZ_SDR_C_OFT 0x84
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#define RSZ_SDR_C_PTR_S 0x88
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#define RSZ_SDR_C_PTR_E 0x8c
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/* Macro for resizer */
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#define RSZ_YUV_Y_MIN 0x40
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#define RSZ_YUV_Y_MAX 0x44
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#define RSZ_YUV_C_MIN 0x48
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#define RSZ_YUV_C_MAX 0x4c
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#define IPIPE_GCK_MMR_DEFAULT 1
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#define IPIPE_GCK_PIX_DEFAULT 0xe
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#define RSZ_GCK_MMR_DEFAULT 1
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#define RSZ_GCK_SDR_DEFAULT 1
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/* LUTDPC */
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#define LUTDPC_TBL_256_EN 0
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#define LUTDPC_INF_TBL_EN 1
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#define LUT_DPC_START_ADDR 0
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#define LUT_DPC_H_POS_MASK 0x1fff
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#define LUT_DPC_V_POS_MASK 0x1fff
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#define LUT_DPC_V_POS_SHIFT 13
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#define LUT_DPC_CORR_METH_SHIFT 26
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#define LUT_DPC_MAX_SIZE 256
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#define LUT_DPC_SIZE_MASK 0x3ff
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/* OTFDPC */
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#define OTFDPC_DPC2_THR_MASK 0xfff
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#define OTF_DET_METHOD_SHIFT 1
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#define OTF_DPC3_0_SHF_MASK 3
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#define OTF_DPC3_0_THR_SHIFT 6
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#define OTF_DPC3_0_THR_MASK 0x3f
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#define OTF_DPC3_0_SLP_MASK 0x3f
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#define OTF_DPC3_0_DET_MASK 0xfff
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#define OTF_DPC3_0_CORR_MASK 0xfff
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/* NF (D2F) */
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#define D2F_SPR_VAL_MASK 0x1f
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#define D2F_SPR_VAL_SHIFT 0
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#define D2F_SHFT_VAL_MASK 3
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#define D2F_SHFT_VAL_SHIFT 5
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#define D2F_SAMPLE_METH_SHIFT 7
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#define D2F_APPLY_LSC_GAIN_SHIFT 8
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#define D2F_USE_SPR_REG_VAL 0
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#define D2F_STR_VAL_MASK 0x1f
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#define D2F_THR_VAL_MASK 0x3ff
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#define D2F_EDGE_DET_THR_MASK 0x7ff
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/* Green Imbalance Correction */
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#define GIC_TYP_SHIFT 0
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#define GIC_THR_SEL_SHIFT 1
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#define GIC_APPLY_LSC_GAIN_SHIFT 2
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#define GIC_GAIN_MASK 0xff
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#define GIC_THR_MASK 0xfff
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#define GIC_SLOPE_MASK 0xfff
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#define GIC_NFGAN_INT_MASK 7
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#define GIC_NFGAN_DECI_MASK 0x1f
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/* WB */
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#define WB_OFFSET_MASK 0xfff
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#define WB_GAIN_INT_MASK 0xf
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#define WB_GAIN_DECI_MASK 0x1ff
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/* CFA */
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#define CFA_HPF_THR_2DIR_MASK 0x1fff
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#define CFA_HPF_SLOPE_2DIR_MASK 0x3ff
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#define CFA_HPF_MIX_THR_2DIR_MASK 0x1fff
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#define CFA_HPF_MIX_SLP_2DIR_MASK 0x3ff
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#define CFA_DIR_THR_2DIR_MASK 0x3ff
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#define CFA_DIR_SLP_2DIR_MASK 0x7f
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#define CFA_ND_WT_2DIR_MASK 0x3f
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#define CFA_DAA_HUE_FRA_MASK 0x3f
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#define CFA_DAA_EDG_THR_MASK 0xff
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#define CFA_DAA_THR_MIN_MASK 0x3ff
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#define CFA_DAA_THR_SLP_MASK 0x3ff
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#define CFA_DAA_SLP_MIN_MASK 0x3ff
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#define CFA_DAA_SLP_SLP_MASK 0x3ff
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#define CFA_DAA_LP_WT_MASK 0x3f
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/* RGB2RGB */
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#define RGB2RGB_1_OFST_MASK 0x1fff
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#define RGB2RGB_1_GAIN_INT_MASK 0xf
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#define RGB2RGB_GAIN_DECI_MASK 0xff
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#define RGB2RGB_2_OFST_MASK 0x7ff
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#define RGB2RGB_2_GAIN_INT_MASK 0x7
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/* Gamma */
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#define GAMMA_BYPR_SHIFT 0
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#define GAMMA_BYPG_SHIFT 1
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#define GAMMA_BYPB_SHIFT 2
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#define GAMMA_TBL_SEL_SHIFT 4
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#define GAMMA_TBL_SIZE_SHIFT 5
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#define GAMMA_MASK 0x3ff
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#define GAMMA_SHIFT 10
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/* 3D LUT */
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#define D3_LUT_ENTRY_MASK 0x3ff
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#define D3_LUT_ENTRY_R_SHIFT 20
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#define D3_LUT_ENTRY_G_SHIFT 10
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#define D3_LUT_ENTRY_B_SHIFT 0
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/* Lumina adj */
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#define LUM_ADJ_CONTR_SHIFT 0
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#define LUM_ADJ_BRIGHT_SHIFT 8
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/* RGB2YCbCr */
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#define RGB2YCBCR_OFST_MASK 0x7ff
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#define RGB2YCBCR_COEF_INT_MASK 0xf
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#define RGB2YCBCR_COEF_DECI_MASK 0xff
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/* GBCE */
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#define GBCE_Y_VAL_MASK 0xff
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#define GBCE_GAIN_VAL_MASK 0x3ff
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#define GBCE_ENTRY_SHIFT 10
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/* Edge Enhancements */
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#define YEE_HALO_RED_EN_SHIFT 1
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#define YEE_HPF_SHIFT_MASK 0xf
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#define YEE_COEF_MASK 0x3ff
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#define YEE_THR_MASK 0x3f
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#define YEE_ES_GAIN_MASK 0xfff
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#define YEE_ES_THR1_MASK 0xfff
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#define YEE_ENTRY_SHIFT 9
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#define YEE_ENTRY_MASK 0x1ff
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/* CAR */
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#define CAR_MF_THR 0xff
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#define CAR_SW1_SHIFT 8
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#define CAR_GAIN1_SHFT_MASK 7
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#define CAR_GAIN_MIN_MASK 0x1ff
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#define CAR_GAIN2_SHFT_MASK 0xf
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#define CAR_HPF_SHIFT_MASK 3
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/* CGS */
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#define CAR_SHIFT_MASK 3
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/* Resizer */
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#define RSZ_BYPASS_SHIFT 1
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#define RSZ_SRC_IMG_FMT_SHIFT 1
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#define RSZ_SRC_Y_C_SEL_SHIFT 2
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#define IPIPE_RSZ_VPS_MASK 0xffff
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#define IPIPE_RSZ_HPS_MASK 0xffff
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#define IPIPE_RSZ_VSZ_MASK 0x1fff
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#define IPIPE_RSZ_HSZ_MASK 0x1fff
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#define RSZ_HPS_MASK 0x1fff
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#define RSZ_VPS_MASK 0x1fff
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#define RSZ_O_HSZ_MASK 0x1fff
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#define RSZ_O_VSZ_MASK 0x1fff
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#define RSZ_V_PHS_MASK 0x3fff
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#define RSZ_V_DIF_MASK 0x3fff
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#define RSZA_H_FLIP_SHIFT 0
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#define RSZA_V_FLIP_SHIFT 1
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#define RSZB_H_FLIP_SHIFT 2
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#define RSZB_V_FLIP_SHIFT 3
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#define RSZ_A 0
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#define RSZ_B 1
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#define RSZ_CEN_SHIFT 1
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#define RSZ_YEN_SHIFT 0
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#define RSZ_TYP_Y_SHIFT 0
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#define RSZ_TYP_C_SHIFT 1
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#define RSZ_LPF_INT_MASK 0x3f
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#define RSZ_LPF_INT_C_SHIFT 6
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#define RSZ_H_PHS_MASK 0x3fff
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#define RSZ_H_DIF_MASK 0x3fff
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#define RSZ_DIFF_DOWN_THR 256
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#define RSZ_DWN_SCALE_AV_SZ_V_SHIFT 3
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#define RSZ_DWN_SCALE_AV_SZ_MASK 7
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#define RSZ_RGB_MSK1_SHIFT 2
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#define RSZ_RGB_MSK0_SHIFT 1
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#define RSZ_RGB_TYP_SHIFT 0
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#define RSZ_RGB_ALPHA_MASK 0xff
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static inline u32 regr_ip(void __iomem *addr, u32 offset)
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{
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return readl(addr + offset);
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}
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static inline void regw_ip(void __iomem *addr, u32 val, u32 offset)
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{
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writel(val, addr + offset);
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}
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static inline u32 w_ip_table(void __iomem *addr, u32 val, u32 offset)
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|
{
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writel(val, addr + offset);
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return val;
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}
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static inline u32 regr_rsz(void __iomem *addr, u32 offset)
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|
{
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|
return readl(addr + offset);
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}
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|
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static inline u32 regw_rsz(void __iomem *addr, u32 val, u32 offset)
|
|
{
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|
writel(val, addr + offset);
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|
|
return val;
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}
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|
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int config_ipipe_hw(struct vpfe_ipipe_device *ipipe);
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int resizer_set_outaddr(void __iomem *rsz_base, struct resizer_params *params,
|
|
int resize_no, unsigned int address);
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int rsz_enable(void __iomem *rsz_base, int rsz_id, int enable);
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|
void rsz_src_enable(void __iomem *rsz_base, int enable);
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|
void rsz_set_in_pix_format(unsigned char y_c);
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int config_rsz_hw(struct vpfe_resizer_device *resizer,
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|
struct resizer_params *config);
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void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
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|
struct vpfe_ipipe_nf *noise_filter);
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|
void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
|
|
struct vpfe_ipipe_rgb2rgb *rgb);
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|
void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
|
|
struct vpfe_ipipe_yuv422_conv *conv);
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|
void ipipe_set_lum_adj_regs(void __iomem *base_addr,
|
|
struct ipipe_lum_adj *lum_adj);
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|
void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
|
|
struct vpfe_ipipe_rgb2yuv *yuv);
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|
void ipipe_set_lutdpc_regs(void __iomem *base_addr,
|
|
void __iomem *isp5_base_addr, struct vpfe_ipipe_lutdpc *lutdpc);
|
|
void ipipe_set_otfdpc_regs(void __iomem *base_addr,
|
|
struct vpfe_ipipe_otfdpc *otfdpc);
|
|
void ipipe_set_3d_lut_regs(void __iomem *base_addr,
|
|
void __iomem *isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d);
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|
void ipipe_set_gamma_regs(void __iomem *base_addr,
|
|
void __iomem *isp5_base_addr, struct vpfe_ipipe_gamma *gamma);
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|
void ipipe_set_ee_regs(void __iomem *base_addr,
|
|
void __iomem *isp5_base_addr, struct vpfe_ipipe_yee *ee);
|
|
void ipipe_set_gbce_regs(void __iomem *base_addr,
|
|
void __iomem *isp5_base_addr, struct vpfe_ipipe_gbce *gbce);
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|
void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
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|
void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
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|
void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
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|
void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
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|
void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
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|
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#endif /* _DAVINCI_VPFE_DM365_IPIPE_HW_H */
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