107 lines
4.3 KiB
C
107 lines
4.3 KiB
C
/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*!
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* @file
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* @brief This file contains macro definitions for accessing ARM TrustZone CryptoCell register space.
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*/
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#ifndef _CC_REGS_H_
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#define _CC_REGS_H_
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#include "cc_bitops.h"
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/* Register Offset macro */
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#define CC_REG_OFFSET(unit_name, reg_name) \
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(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
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#define CC_REG_BIT_SHIFT(reg_name, field_name) \
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(DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT)
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/* Register Offset macros (from registers base address in host) */
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#include "dx_reg_base_host.h"
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/* Read-Modify-Write a field of a register */
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#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \
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do { \
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uint32_t regVal; \
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regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName)); \
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CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \
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WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal); \
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} while (0)
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/* Registers address macros for ENV registers (development FPGA only) */
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#ifdef DX_BASE_ENV_REGS
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/* This offset should be added to mapping address of DX_BASE_ENV_REGS */
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#define CC_ENV_REG_OFFSET(reg_name) (DX_ENV_ ## reg_name ## _REG_OFFSET)
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#endif /*DX_BASE_ENV_REGS*/
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/*! Bit fields get */
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#define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \
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(DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
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reg_val /*!< \internal Optimization for 32b fields */ : \
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BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
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/*! Bit fields access */
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#define CC_REG_FLD_GET2(unit_name, reg_name, fld_name, reg_val) \
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(CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \
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reg_val /*!< \internal Optimization for 32b fields */ : \
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BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
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/* yael TBD !!! - *
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* all HW includes should start with CC_ and not DX_ !! */
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/*! Bit fields set */
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#define CC_REG_FLD_SET( \
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unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
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do { \
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if (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
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reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
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else \
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BITFIELD_SET(reg_shadow_var, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
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new_fld_val); \
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} while (0)
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/*! Bit fields set */
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#define CC_REG_FLD_SET2( \
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unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \
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do { \
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if (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \
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reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\
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else \
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BITFIELD_SET(reg_shadow_var, \
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CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
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CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \
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new_fld_val); \
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} while (0)
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/* Usage example:
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uint32_t reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
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CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
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CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
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WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
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*/
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#endif /*_CC_REGS_H_*/
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