170 lines
4.1 KiB
C
170 lines
4.1 KiB
C
#ifndef _ASM_METAG_IO_H
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#define _ASM_METAG_IO_H
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#include <linux/types.h>
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#include <asm/pgtable-bits.h>
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#define IO_SPACE_LIMIT 0
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#define page_to_bus page_to_phys
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#define bus_to_page phys_to_page
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/*
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* Generic I/O
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*/
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 ret;
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asm volatile("GETB %0,[%1]"
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: "=da" (ret)
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: "da" (addr)
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: "memory");
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return ret;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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asm volatile("GETW %0,[%1]"
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: "=da" (ret)
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: "da" (addr)
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: "memory");
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return ret;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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asm volatile("GETD %0,[%1]"
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: "=da" (ret)
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: "da" (addr)
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: "memory");
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return ret;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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asm volatile("GETL %0,%t0,[%1]"
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: "=da" (ret)
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: "da" (addr)
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: "memory");
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return ret;
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}
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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asm volatile("SETB [%0],%1"
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:
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: "da" (addr),
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"da" (b)
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: "memory");
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 b, volatile void __iomem *addr)
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{
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asm volatile("SETW [%0],%1"
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:
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: "da" (addr),
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"da" (b)
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: "memory");
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 b, volatile void __iomem *addr)
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{
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asm volatile("SETD [%0],%1"
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:
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: "da" (addr),
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"da" (b)
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: "memory");
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
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{
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asm volatile("SETL [%0],%1,%t1"
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:
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: "da" (addr),
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"da" (b)
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: "memory");
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}
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/*
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* The generic io.h can define all the other generic accessors
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*/
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#include <asm-generic/io.h>
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/*
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* Despite being a 32bit architecture, Meta can do 64bit memory accesses
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* (assuming the bus supports it).
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*/
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#define readq __raw_readq
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#define writeq __raw_writeq
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/*
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* Meta specific I/O for accessing non-MMU areas.
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*
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* These can be provided with a physical address rather than an __iomem pointer
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* and should only be used by core architecture code for accessing fixed core
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* registers. Generic drivers should use ioremap and the generic I/O accessors.
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*/
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#define metag_in8(addr) __raw_readb((volatile void __iomem *)(addr))
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#define metag_in16(addr) __raw_readw((volatile void __iomem *)(addr))
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#define metag_in32(addr) __raw_readl((volatile void __iomem *)(addr))
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#define metag_in64(addr) __raw_readq((volatile void __iomem *)(addr))
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#define metag_out8(b, addr) __raw_writeb(b, (volatile void __iomem *)(addr))
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#define metag_out16(b, addr) __raw_writew(b, (volatile void __iomem *)(addr))
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#define metag_out32(b, addr) __raw_writel(b, (volatile void __iomem *)(addr))
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#define metag_out64(b, addr) __raw_writeq(b, (volatile void __iomem *)(addr))
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/*
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* io remapping functions
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*/
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extern void __iomem *__ioremap(unsigned long offset,
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size_t size, unsigned long flags);
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extern void __iounmap(void __iomem *addr);
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/**
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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__ioremap((offset), (size), 0)
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#define ioremap_nocache(offset, size) \
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__ioremap((offset), (size), 0)
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#define ioremap_cached(offset, size) \
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__ioremap((offset), (size), _PAGE_CACHEABLE)
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#define ioremap_wc(offset, size) \
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__ioremap((offset), (size), _PAGE_WR_COMBINE)
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#define ioremap_wt(offset, size) \
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__ioremap((offset), (size), 0)
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#define iounmap(addr) \
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__iounmap(addr)
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#endif /* _ASM_METAG_IO_H */
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