271 lines
8.9 KiB
C
271 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Macros and functions to manipulate Meta page tables.
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*/
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#ifndef _METAG_PGTABLE_H
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#define _METAG_PGTABLE_H
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#include <asm/pgtable-bits.h>
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#define __ARCH_USE_5LEVEL_HACK
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#include <asm-generic/pgtable-nopmd.h>
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/* Invalid regions on Meta: 0x00000000-0x001FFFFF and 0xFFFF0000-0xFFFFFFFF */
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#if PAGE_OFFSET >= LINGLOBAL_BASE
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#define CONSISTENT_START 0xF7000000
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#define CONSISTENT_END 0xF73FFFFF
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#define VMALLOC_START 0xF8000000
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#define VMALLOC_END 0xFFFEFFFF
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#else
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#define CONSISTENT_START 0x77000000
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#define CONSISTENT_END 0x773FFFFF
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#define VMALLOC_START 0x78000000
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#define VMALLOC_END 0x7FFFFFFF
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#endif
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* Meta, we use that, but "fold" the mid level into the top-level page
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* table.
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*/
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/* PGDIR_SHIFT determines the size of the area a second-level page table can
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* map. This is always 4MB.
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*/
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use a two-level, so
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* we don't really have any PMD directory physically. First level tables
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* always map 2Gb (local or global) at a granularity of 4MB, second-level
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* tables map 4MB with a granularity between 4MB and 4kB (between 1 and
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* 1024 entries).
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*/
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#define PTRS_PER_PTE (PGDIR_SIZE/PAGE_SIZE)
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#define HPTRS_PER_PTE (PGDIR_SIZE/HPAGE_SIZE)
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#define PTRS_PER_PGD 512
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#define USER_PTRS_PER_PGD 256
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#define FIRST_USER_ADDRESS META_MEMORY_BASE
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#define FIRST_USER_PGD_NR pgd_index(FIRST_USER_ADDRESS)
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHEABLE)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
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_PAGE_ACCESSED | _PAGE_CACHEABLE)
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#define PAGE_SHARED_C PAGE_SHARED
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHEABLE)
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#define PAGE_COPY_C PAGE_COPY
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHEABLE)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_WRITE | \
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_PAGE_CACHEABLE | _PAGE_KERNEL)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY
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#define __P110 PAGE_COPY_C
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#define __P111 PAGE_COPY_C
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY
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#define __S110 PAGE_SHARED_C
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#define __S111 PAGE_SHARED_C
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#ifndef __ASSEMBLY__
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#include <asm/page.h>
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/* zero page used for uninitialized stuff */
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extern unsigned long empty_zero_page;
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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/* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
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#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_bad(x) ((pmd_val(x) & ~(PAGE_MASK | _PAGE_SZ_MASK)) \
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!= (_PAGE_TABLE & ~_PAGE_SZ_MASK))
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#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
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#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_special(pte_t pte) { return 0; }
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static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= (~_PAGE_WRITE); return pte; }
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static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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static inline pte_t pte_mkhuge(pte_t pte) { return pte; }
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/*
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* Macro and implementation to make a page protection as uncacheable.
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*/
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#define pgprot_writecombine(prot) \
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__pgprot(pgprot_val(prot) & ~(_PAGE_CACHE_CTRL1 | _PAGE_CACHE_CTRL0))
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#define pgprot_noncached(prot) \
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__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE)
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
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return pte;
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}
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static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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unsigned long paddr = pmd_val(pmd) & PAGE_MASK;
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if (!paddr)
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return 0;
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return (unsigned long)__va(paddr);
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}
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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#define pmd_page_shift(pmd) (12 + ((pmd_val(pmd) & _PAGE_SZ_MASK) \
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>> _PAGE_SZ_SHIFT))
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#define pmd_num_ptrs(pmd) (PGDIR_SIZE >> pmd_page_shift(pmd))
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/*
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* Each pgd is only 2k, mapping 2Gb (local or global). If we're in global
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* space drop the top bit before indexing the pgd.
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*/
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#if PAGE_OFFSET >= LINGLOBAL_BASE
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#define pgd_index(address) ((((address) & ~0x80000000) >> PGDIR_SHIFT) \
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& (PTRS_PER_PGD-1))
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#else
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#endif
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/* Find an entry in the second-level page table.. */
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#if !defined(CONFIG_HUGETLB_PAGE)
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/* all pages are of size (1 << PAGE_SHIFT), so no need to read 1st level pt */
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# define pte_index(pmd, address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#else
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/* some pages are huge, so read 1st level pt to find out */
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# define pte_index(pmd, address) \
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(((address) >> pmd_page_shift(pmd)) & (pmd_num_ptrs(pmd) - 1))
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#endif
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(*(dir), address))
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#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
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#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Meta doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *pte)
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{
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}
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/*
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* Encode and decode a swap entry (must be !pte_none(e) && !pte_present(e))
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* Since PAGE_PRESENT is bit 1, we can use the bits above that.
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*/
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#define __swp_type(x) (((x).val >> 1) & 0xff)
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#define __swp_offset(x) ((x).val >> 10)
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#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | \
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((offset) << 10) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define kern_addr_valid(addr) (1)
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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void paging_init(unsigned long mem_end);
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#ifdef CONFIG_METAG_META12
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/* This is a workaround for an issue in Meta 1 cores. These cores cache
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* invalid entries in the TLB so we always need to flush whenever we add
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* a new pte. Unfortunately we can only flush the whole TLB not shoot down
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* single entries so this is sub-optimal. This implementation ensures that
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* we will get a flush at the second attempt, so we may still get repeated
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* faults, we just don't overflow the kernel stack handling them.
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*/
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
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({ \
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int __changed = !pte_same(*(__ptep), __entry); \
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if (__changed) { \
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set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
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} \
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flush_tlb_page(__vma, __address); \
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__changed; \
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})
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#endif
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#include <asm-generic/pgtable.h>
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#endif /* __ASSEMBLY__ */
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#endif /* _METAG_PGTABLE_H */
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