161 lines
3.9 KiB
Plaintext
161 lines
3.9 KiB
Plaintext
--- scripts/dtc/include-prefixes/arm/imx6qdl-sabresd.dtsi 2017-08-30 04:32:30.000000000 -0400
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+++ scripts/dtc/include-prefixes/arm/imx6qdl-sabresd.dtsi 2017-09-03 16:56:17.000000000 -0400
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@@ -10,6 +10,7 @@
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* http://www.gnu.org/copyleft/gpl.html
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*/
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+#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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@@ -146,6 +147,36 @@
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};
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};
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+&ipu1_csi0_from_ipu1_csi0_mux {
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+ bus-width = <8>;
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+ data-shift = <12>; /* Lines 19:12 used */
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+ hsync-active = <1>;
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+ vsync-active = <1>;
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+};
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+
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+&ipu1_csi0_mux_from_parallel_sensor {
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+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
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+};
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+
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+&ipu1_csi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
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+};
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+
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+&mipi_csi {
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+ status = "okay";
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+
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+ port@0 {
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+ reg = <0>;
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+
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+ mipi_csi2_in: endpoint {
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+ remote-endpoint = <&ov5640_to_mipi_csi2>;
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+ clock-lanes = <0>;
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+ data-lanes = <1 2>;
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+ };
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+ };
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+};
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+
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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@@ -178,7 +209,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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- phy-reset-gpios = <&gpio1 25 0>;
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+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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@@ -213,7 +244,32 @@
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0x8014 /* 4:FN_DMICCDAT */
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0x0000 /* 5:Default */
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>;
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- };
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+ };
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+
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+ ov5642: camera@3c {
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+ compatible = "ovti,ov5642";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ov5642>;
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+ clocks = <&clks IMX6QDL_CLK_CKO>;
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+ clock-names = "xclk";
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+ reg = <0x3c>;
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+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
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+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
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+ rev B board is VGEN5 */
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+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
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+ powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
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+ status = "disabled";
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+
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+ port {
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+ ov5642_to_ipu1_csi0_mux: endpoint {
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+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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+ bus-width = <8>;
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+ hsync-active = <1>;
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+ vsync-active = <1>;
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+ };
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+ };
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+ };
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};
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&i2c2 {
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@@ -222,6 +278,32 @@
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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+ ov5640: camera@3c {
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+ compatible = "ovti,ov5640";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ov5640>;
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+ reg = <0x3c>;
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+ clocks = <&clks IMX6QDL_CLK_CKO>;
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+ clock-names = "xclk";
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+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
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+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
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+ rev B board is VGEN5 */
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+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
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+ powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
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+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
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+
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+ port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ov5640_to_mipi_csi2: endpoint {
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+ remote-endpoint = <&mipi_csi2_in>;
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+ clock-lanes = <0>;
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+ data-lanes = <1 2>;
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+ };
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+ };
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+ };
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+
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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@@ -425,6 +507,36 @@
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>;
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};
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+ pinctrl_ipu1_csi0: ipu1csi0grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
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+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
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+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
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+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
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+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
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+ >;
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+ };
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+
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+ pinctrl_ov5640: ov5640grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
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+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
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+ >;
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+ };
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+
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+ pinctrl_ov5642: ov5642grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
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+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
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+ >;
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+ };
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+
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
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