diff --git a/patches/5.3/0008-use-legacy-i915-driver.patch b/patches/5.3/0008-use-legacy-i915-driver.patch
index 6bead63b3..b843d08f5 100644
--- a/patches/5.3/0008-use-legacy-i915-driver.patch
+++ b/patches/5.3/0008-use-legacy-i915-driver.patch
@@ -5186,16 +5186,16 @@ index 000000000000..de5347725564
 +#define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 +#define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 +
-+#define OP_3DSTATE_VF_INSTANCING 		OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
-+#define OP_3DSTATE_VF_SGVS  			OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
-+#define OP_3DSTATE_VF_TOPOLOGY   		OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
-+#define OP_3DSTATE_WM_CHROMAKEY   		OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
-+#define OP_3DSTATE_PS_BLEND   			OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
-+#define OP_3DSTATE_WM_DEPTH_STENCIL   		OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
-+#define OP_3DSTATE_PS_EXTRA   			OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
-+#define OP_3DSTATE_RASTER   			OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
-+#define OP_3DSTATE_SBE_SWIZ   			OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
-+#define OP_3DSTATE_WM_HZ_OP   			OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
++#define OP_3DSTATE_VF_INSTANCING		OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
++#define OP_3DSTATE_VF_SGVS			OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
++#define OP_3DSTATE_VF_TOPOLOGY			OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
++#define OP_3DSTATE_WM_CHROMAKEY			OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
++#define OP_3DSTATE_PS_BLEND			OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
++#define OP_3DSTATE_WM_DEPTH_STENCIL		OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
++#define OP_3DSTATE_PS_EXTRA			OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
++#define OP_3DSTATE_RASTER			OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
++#define OP_3DSTATE_SBE_SWIZ			OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
++#define OP_3DSTATE_WM_HZ_OP			OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 +#define OP_3DSTATE_COMPONENT_PACKING		OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 +
 +#define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
@@ -41810,7 +41810,7 @@ index 000000000000..066fd2a12851
 +#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
 +#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
 +
-+#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
++#define HAS_FW_BLC(dev_priv)	(INTEL_GEN(dev_priv) > 2)
 +#define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_fbc)
 +#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
 +
@@ -73686,7 +73686,7 @@ new file mode 100644
 index 000000000000..3f14e9881a0d
 --- /dev/null
 +++ b/drivers/gpu/drm/i915_legacy/i915_params.h
-@@ -0,0 +1,94 @@
+@@ -0,0 +1,93 @@
 +/*
 + * Copyright © 2015 Intel Corporation
 + *
@@ -73780,7 +73780,6 @@ index 000000000000..3f14e9881a0d
 +void i915_params_free(struct i915_params *params);
 +
 +#endif
-+
 diff --git a/drivers/gpu/drm/i915_legacy/i915_pci.c b/drivers/gpu/drm/i915_legacy/i915_pci.c
 new file mode 100644
 index 000000000000..f893c2cbce15
@@ -87571,7 +87570,7 @@ index 000000000000..cf748b80e640
 +#define _PIPEC_CHICKEN				0x72038
 +#define PIPE_CHICKEN(pipe)			_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
 +							   _PIPEB_CHICKEN)
-+#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
++#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU	(1 << 15)
 +#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 +
 +/* PCH */
@@ -140235,10 +140234,10 @@ index 000000000000..560274d1c50b
 +	/*
 +	 * There are four kinds of DP registers:
 +	 *
-+	 * 	IBX PCH
-+	 * 	SNB CPU
++	 *	IBX PCH
++	 *	SNB CPU
 +	 *	IVB CPU
-+	 * 	CPT PCH
++	 *	CPT PCH
 +	 *
 +	 * IBX PCH and CPU are the same for almost everything,
 +	 * except that the CPU DP PLL is configured in this
@@ -140303,7 +140302,7 @@ index 000000000000..560274d1c50b
 +}
 +
 +#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
-+#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
++#define IDLE_ON_VALUE		(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 +
 +#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 +#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
@@ -220078,7 +220077,7 @@ index 000000000000..d1d51e1121e2
 +
 +/**
 + * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
-+ * 				    a register
++ *				    a register
 + * @uncore: pointer to struct intel_uncore
 + * @reg: register in question
 + * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE