Update v5.17 patches
Changes:
- Move IOMMU fix for IPU to camera patches.
- Refactor Surface Aggregator client device hubs and client device registration.
(PR: https://github.com/linux-surface/kernel/pull/126)
- Remove code duplication
- Fix potential rare race condition
- Prepare for DT/OF support
Links:
- kernel: 27304f1c05
This commit is contained in:
Maximilian Luz
parent
6f40ab3d86
commit
2b99605bb2
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@ -5,6 +5,7 @@ CONFIG_SURFACE_AGGREGATOR=m
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CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION=n
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CONFIG_SURFACE_AGGREGATOR_BUS=y
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CONFIG_SURFACE_AGGREGATOR_CDEV=m
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CONFIG_SURFACE_AGGREGATOR_HUB=m
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CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
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CONFIG_SURFACE_ACPI_NOTIFY=m
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@ -1,4 +1,4 @@
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From ab3cf5956cb42d85e1d683e40ba9a7e65cdc0d3c Mon Sep 17 00:00:00 2001
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From 646a8f056267c0c6efe791753f05c202d5f991c1 Mon Sep 17 00:00:00 2001
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From: Tsuchiya Yuto <kitakar@gmail.com>
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Date: Sun, 18 Oct 2020 16:42:44 +0900
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Subject: [PATCH] (surface3-oemb) add DMI matches for Surface 3 with broken DMI
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@ -1,4 +1,4 @@
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From 64202a02564117e9b755fada551e52fbca7c6ad6 Mon Sep 17 00:00:00 2001
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From 8d5bbcb596dc777e691b738c90fdde519d5ff70b Mon Sep 17 00:00:00 2001
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From: Tsuchiya Yuto <kitakar@gmail.com>
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Date: Tue, 29 Sep 2020 17:32:22 +0900
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Subject: [PATCH] mwifiex: pcie: add reset_wsid quirk for Surface 3
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@ -183,7 +183,7 @@ index 8ec4176d698f..25370c5a4f59 100644
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--
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2.36.1
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From 6c4b332c571a9549c669e33593fc33e2857fe9c2 Mon Sep 17 00:00:00 2001
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From aa1d32ead69fc367cfe67296dda751a5e40b342f Mon Sep 17 00:00:00 2001
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From: Tsuchiya Yuto <kitakar@gmail.com>
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Date: Wed, 30 Sep 2020 18:08:24 +0900
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Subject: [PATCH] mwifiex: pcie: (OEMB) add quirk for Surface 3 with broken DMI
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@ -245,7 +245,7 @@ index 563dd0d5ac79..32e2f000e57b 100644
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--
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2.36.1
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From 3f8851f15a581361c9d9f754ec6cdd61b9fb7482 Mon Sep 17 00:00:00 2001
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From 4ac41e0c2d8fe11f20a5f79a0bfe0f56db7a5f2e Mon Sep 17 00:00:00 2001
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From: Tsuchiya Yuto <kitakar@gmail.com>
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Date: Sun, 4 Oct 2020 00:11:49 +0900
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Subject: [PATCH] mwifiex: pcie: disable bridge_d3 for Surface gen4+
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@ -400,7 +400,7 @@ index 25370c5a4f59..a1de111ad1db 100644
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--
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2.36.1
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From a018459a97fb908a8a8dad68cf9aa590c3906ca1 Mon Sep 17 00:00:00 2001
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From bfcc84af31034dbdd24013dc9a26abe285b40f6c Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl>
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Date: Tue, 3 Nov 2020 13:28:04 +0100
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Subject: [PATCH] mwifiex: Add quirk resetting the PCI bridge on MS Surface
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@ -567,7 +567,7 @@ index a1de111ad1db..0e429779bb04 100644
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--
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2.36.1
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From 1c2eb6887e0b6083873235c84e76064c2d11a92a Mon Sep 17 00:00:00 2001
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From 58c6afc494c4e3b99d616ecbcaaae4fc2a2793f3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl>
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Date: Thu, 25 Mar 2021 11:33:02 +0100
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Subject: [PATCH] Bluetooth: btusb: Lower passive lescan interval on Marvell
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@ -645,7 +645,7 @@ index 42234d5f602d..72202a744564 100644
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--
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2.36.1
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From fab12336aec2d01fa54360116f7c4d5b2d386b4c Mon Sep 17 00:00:00 2001
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From 2fca431e32e851a81ec218ef3dc87563d7cd0e68 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl>
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Date: Tue, 10 Nov 2020 12:49:56 +0100
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Subject: [PATCH] mwifiex: Use non-posted PCI register writes
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@ -1,4 +1,4 @@
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From 896a491d6dc5b3788255ad869137e96464c8ec32 Mon Sep 17 00:00:00 2001
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From d4c4b533922f980a4cf0ad48db72506b3cba3a01 Mon Sep 17 00:00:00 2001
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From: Maximilian Luz <luzmaximilian@gmail.com>
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Date: Sat, 27 Feb 2021 00:45:52 +0100
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Subject: [PATCH] ath10k: Add module parameters to override board files
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@ -1,4 +1,4 @@
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From 04b2ff1b78b0f36536bad0e3e193951d5028d2e9 Mon Sep 17 00:00:00 2001
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From e2a9cc1c420b8f9584c85914b6b8c8cb38b2fecc Mon Sep 17 00:00:00 2001
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From: Dorian Stoll <dorian.stoll@tmsp.io>
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Date: Thu, 30 Jul 2020 13:21:53 +0200
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Subject: [PATCH] misc: mei: Add missing IPTS device IDs
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@ -36,7 +36,7 @@ index a738253dbd05..4e1c3fe09e53 100644
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--
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2.36.1
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From 2cff5747cece8b1537ee34e96d2a94ff5909c9f0 Mon Sep 17 00:00:00 2001
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From c7d40fe3f9a803b17f8529caa7bc4b58c0a2e66a Mon Sep 17 00:00:00 2001
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From: Dorian Stoll <dorian.stoll@tmsp.io>
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Date: Thu, 6 Aug 2020 11:20:41 +0200
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Subject: [PATCH] misc: Add support for Intel Precise Touch & Stylus
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@ -1501,116 +1501,7 @@ index 000000000000..53fb86a88f97
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--
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2.36.1
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From 729bc1af3979f4826b11db82d5353a5f85971d3e Mon Sep 17 00:00:00 2001
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From: zouxiaoh <xiaohong.zou@intel.com>
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Date: Fri, 25 Jun 2021 08:52:59 +0800
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Subject: [PATCH] iommu: intel-ipu: use IOMMU passthrough mode for Intel IPUs
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Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
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The IPU driver allocates its own page table that is not mapped
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via the DMA, and thus the Intel IOMMU driver blocks access giving
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this error: DMAR: DRHD: handling fault status reg 3 DMAR:
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[DMA Read] Request device [00:05.0] PASID ffffffff
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fault addr 76406000 [fault reason 06] PTE Read access is not set
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As IPU is not an external facing device which is not risky, so use
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IOMMU passthrough mode for Intel IPUs.
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Change-Id: I6dcccdadac308cf42e20a18e1b593381391e3e6b
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Depends-On: Iacd67578e8c6a9b9ac73285f52b4081b72fb68a6
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Tracked-On: #JIITL8-411
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Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
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Signed-off-by: zouxiaoh <xiaohong.zou@intel.com>
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Signed-off-by: Xu Chongyang <chongyang.xu@intel.com>
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Patchset: ipts
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---
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drivers/iommu/intel/iommu.c | 29 +++++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
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index ab2273300346..c1c0b111e512 100644
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--- a/drivers/iommu/intel/iommu.c
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+++ b/drivers/iommu/intel/iommu.c
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@@ -57,6 +57,12 @@
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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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+#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \
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+ ((pdev)->device == 0x9a19 || \
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+ (pdev)->device == 0x9a39 || \
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+ (pdev)->device == 0x4e19 || \
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+ (pdev)->device == 0x465d || \
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+ (pdev)->device == 0x1919))
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START (0xfee00000)
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@@ -332,12 +338,14 @@ int intel_iommu_enabled = 0;
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EXPORT_SYMBOL_GPL(intel_iommu_enabled);
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static int dmar_map_gfx = 1;
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+static int dmar_map_ipu = 1;
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static int intel_iommu_superpage = 1;
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static int iommu_identity_mapping;
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static int iommu_skip_te_disable;
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#define IDENTMAP_GFX 2
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#define IDENTMAP_AZALIA 4
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+#define IDENTMAP_IPU 8
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int intel_iommu_gfx_mapped;
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EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
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@@ -2987,6 +2995,9 @@ static int device_def_domain_type(struct device *dev)
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if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
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return IOMMU_DOMAIN_IDENTITY;
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+
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+ if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev))
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+ return IOMMU_DOMAIN_IDENTITY;
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}
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return 0;
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@@ -3423,6 +3434,9 @@ static int __init init_dmars(void)
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if (!dmar_map_gfx)
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iommu_identity_mapping |= IDENTMAP_GFX;
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+ if (!dmar_map_ipu)
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+ iommu_identity_mapping |= IDENTMAP_IPU;
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+
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check_tylersburg_isoch();
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ret = si_domain_init(hw_pass_through);
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@@ -5664,6 +5678,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev)
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dmar_map_gfx = 0;
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}
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+static void quirk_iommu_ipu(struct pci_dev *dev)
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+{
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+ if (!IS_INTEL_IPU(dev))
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+ return;
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+
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+ if (risky_device(dev))
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+ return;
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+
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+ pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n");
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+ dmar_map_ipu = 0;
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+}
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+
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/* G4x/GM45 integrated gfx dmar support is totally busted. */
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx);
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@@ -5699,6 +5725,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
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+/* disable IPU dmar support */
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu);
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+
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static void quirk_iommu_rwbf(struct pci_dev *dev)
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{
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if (risky_device(dev))
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--
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2.36.1
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From 8e0d67470adea3b5f4cd744fa863292c8835f641 Mon Sep 17 00:00:00 2001
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From af203d5ea529b8d75dfcb53b993bd7c060d258a2 Mon Sep 17 00:00:00 2001
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From: Liban Hannan <liban.p@gmail.com>
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Date: Tue, 12 Apr 2022 23:31:12 +0100
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Subject: [PATCH] iommu: ipts: use IOMMU passthrough mode for IPTS
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@ -1632,37 +1523,36 @@ Patchset: ipts
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1 file changed, 24 insertions(+)
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diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
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index c1c0b111e512..4d28bcc35dfb 100644
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index ab2273300346..a91eed82bb39 100644
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--- a/drivers/iommu/intel/iommu.c
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+++ b/drivers/iommu/intel/iommu.c
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@@ -63,6 +63,8 @@
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(pdev)->device == 0x4e19 || \
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(pdev)->device == 0x465d || \
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(pdev)->device == 0x1919))
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@@ -57,6 +57,8 @@
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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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+#define IS_IPTS(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \
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+ ((pdev)->device == 0x9d3e))
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START (0xfee00000)
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@@ -339,6 +341,7 @@ EXPORT_SYMBOL_GPL(intel_iommu_enabled);
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@@ -332,12 +334,14 @@ int intel_iommu_enabled = 0;
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EXPORT_SYMBOL_GPL(intel_iommu_enabled);
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static int dmar_map_gfx = 1;
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static int dmar_map_ipu = 1;
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+static int dmar_map_ipts = 1;
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static int intel_iommu_superpage = 1;
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static int iommu_identity_mapping;
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static int iommu_skip_te_disable;
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@@ -346,6 +349,7 @@ static int iommu_skip_te_disable;
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#define IDENTMAP_GFX 2
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#define IDENTMAP_AZALIA 4
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#define IDENTMAP_IPU 8
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+#define IDENTMAP_IPTS 16
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int intel_iommu_gfx_mapped;
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EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
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@@ -2998,6 +3002,9 @@ static int device_def_domain_type(struct device *dev)
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@@ -2987,6 +2991,9 @@ static int device_def_domain_type(struct device *dev)
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if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev))
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if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
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return IOMMU_DOMAIN_IDENTITY;
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+
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+ if ((iommu_identity_mapping & IDENTMAP_IPTS) && IS_IPTS(pdev))
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@ -1670,9 +1560,9 @@ index c1c0b111e512..4d28bcc35dfb 100644
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}
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return 0;
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@@ -3437,6 +3444,9 @@ static int __init init_dmars(void)
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if (!dmar_map_ipu)
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iommu_identity_mapping |= IDENTMAP_IPU;
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@@ -3423,6 +3430,9 @@ static int __init init_dmars(void)
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if (!dmar_map_gfx)
|
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iommu_identity_mapping |= IDENTMAP_GFX;
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|
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+ if (!dmar_map_ipts)
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+ iommu_identity_mapping |= IDENTMAP_IPTS;
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|
|
@ -1680,8 +1570,8 @@ index c1c0b111e512..4d28bcc35dfb 100644
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check_tylersburg_isoch();
|
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|
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ret = si_domain_init(hw_pass_through);
|
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@@ -5690,6 +5700,17 @@ static void quirk_iommu_ipu(struct pci_dev *dev)
|
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dmar_map_ipu = 0;
|
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@@ -5664,6 +5674,17 @@ static void quirk_iommu_igfx(struct pci_dev *dev)
|
||||
dmar_map_gfx = 0;
|
||||
}
|
||||
|
||||
+static void quirk_iommu_ipts(struct pci_dev *dev)
|
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|
|
@ -1698,9 +1588,9 @@ index c1c0b111e512..4d28bcc35dfb 100644
|
|||
/* G4x/GM45 integrated gfx dmar support is totally busted. */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx);
|
||||
@@ -5728,6 +5749,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
|
||||
/* disable IPU dmar support */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu);
|
||||
@@ -5699,6 +5720,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
|
||||
|
||||
+/* disable IPTS dmar support */
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9D3E, quirk_iommu_ipts);
|
||||
|
|
|
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File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,4 @@
|
|||
From 8d0873dd7c49de7c592fa0dcae40ebabb84f9217 Mon Sep 17 00:00:00 2001
|
||||
From 25d1faa2928596cc4902653225e57741688730a4 Mon Sep 17 00:00:00 2001
|
||||
From: Maximilian Luz <luzmaximilian@gmail.com>
|
||||
Date: Sat, 25 Jul 2020 17:19:53 +0200
|
||||
Subject: [PATCH] i2c: acpi: Implement RawBytes read access
|
||||
|
|
@ -110,7 +110,7 @@ index 85ed4c1d4924..942c1c9a4ea5 100644
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|||
--
|
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2.36.1
|
||||
|
||||
From 5992742dd066ad33a1bd7a274b24a1681306151a Mon Sep 17 00:00:00 2001
|
||||
From 2ec19064dafe6c2150f2fab606ad38fcfdc757d0 Mon Sep 17 00:00:00 2001
|
||||
From: Maximilian Luz <luzmaximilian@gmail.com>
|
||||
Date: Sat, 13 Feb 2021 16:41:18 +0100
|
||||
Subject: [PATCH] platform/surface: Add driver for Surface Book 1 dGPU switch
|
||||
|
|
@ -133,10 +133,10 @@ Patchset: surface-sam-over-hid
|
|||
create mode 100644 drivers/platform/surface/surfacebook1_dgpu_switch.c
|
||||
|
||||
diff --git a/drivers/platform/surface/Kconfig b/drivers/platform/surface/Kconfig
|
||||
index 9c228090c35b..c6c3c9bd3b57 100644
|
||||
index c685ec440535..3d3659b87ba4 100644
|
||||
--- a/drivers/platform/surface/Kconfig
|
||||
+++ b/drivers/platform/surface/Kconfig
|
||||
@@ -106,6 +106,13 @@ config SURFACE_AGGREGATOR_REGISTRY
|
||||
@@ -133,6 +133,13 @@ config SURFACE_AGGREGATOR_REGISTRY
|
||||
the respective client devices. Drivers for these devices still need to
|
||||
be selected via the other options.
|
||||
|
||||
|
|
@ -151,12 +151,12 @@ index 9c228090c35b..c6c3c9bd3b57 100644
|
|||
tristate "Surface DTX (Detachment System) Driver"
|
||||
depends on SURFACE_AGGREGATOR
|
||||
diff --git a/drivers/platform/surface/Makefile b/drivers/platform/surface/Makefile
|
||||
index 6d9291c993c4..9eb3a7e6382c 100644
|
||||
index fccd33e6780d..20408730f425 100644
|
||||
--- a/drivers/platform/surface/Makefile
|
||||
+++ b/drivers/platform/surface/Makefile
|
||||
@@ -11,6 +11,7 @@ obj-$(CONFIG_SURFACE_ACPI_NOTIFY) += surface_acpi_notify.o
|
||||
obj-$(CONFIG_SURFACE_AGGREGATOR) += aggregator/
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_SURFACE_AGGREGATOR) += aggregator/
|
||||
obj-$(CONFIG_SURFACE_AGGREGATOR_CDEV) += surface_aggregator_cdev.o
|
||||
obj-$(CONFIG_SURFACE_AGGREGATOR_HUB) += surface_aggregator_hub.o
|
||||
obj-$(CONFIG_SURFACE_AGGREGATOR_REGISTRY) += surface_aggregator_registry.o
|
||||
+obj-$(CONFIG_SURFACE_BOOK1_DGPU_SWITCH) += surfacebook1_dgpu_switch.o
|
||||
obj-$(CONFIG_SURFACE_DTX) += surface_dtx.o
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From e545e04dd39aec84ac1c3d7dcd11fb5399748e59 Mon Sep 17 00:00:00 2001
|
||||
From fa15e994d04fdd10bc3b0201d27574206ba44662 Mon Sep 17 00:00:00 2001
|
||||
From: Maximilian Luz <luzmaximilian@gmail.com>
|
||||
Date: Wed, 27 Oct 2021 00:56:11 +0200
|
||||
Subject: [PATCH] platform/surface: gpe: Add support for Surface Pro 8
|
||||
|
|
@ -14,7 +14,7 @@ Patchset: surface-gpe
|
|||
1 file changed, 8 insertions(+)
|
||||
|
||||
diff --git a/drivers/platform/surface/surface_gpe.c b/drivers/platform/surface/surface_gpe.c
|
||||
index c1775db29efb..ec66fde28e75 100644
|
||||
index b7e48ba100b6..27365cbe1ee9 100644
|
||||
--- a/drivers/platform/surface/surface_gpe.c
|
||||
+++ b/drivers/platform/surface/surface_gpe.c
|
||||
@@ -99,6 +99,14 @@ static const struct dmi_system_id dmi_lid_device_table[] = {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From c0e0c71b09f1623e3c831335459d984ce7530569 Mon Sep 17 00:00:00 2001
|
||||
From 0e6a0910bdec9c3b4d9658207c7b2cde6d86d375 Mon Sep 17 00:00:00 2001
|
||||
From: Sachi King <nakato@nakato.io>
|
||||
Date: Tue, 5 Oct 2021 00:05:09 +1100
|
||||
Subject: [PATCH] Input: soc_button_array - support AMD variant Surface devices
|
||||
|
|
@ -75,7 +75,7 @@ index cb6ec59a045d..4e8944f59def 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From c03c5f3ea363be1167c8ede10bce82ae85ed1ca9 Mon Sep 17 00:00:00 2001
|
||||
From 6224cf2d064ad98e8aa6153be11cbee3fc760cdc Mon Sep 17 00:00:00 2001
|
||||
From: Sachi King <nakato@nakato.io>
|
||||
Date: Tue, 5 Oct 2021 00:22:57 +1100
|
||||
Subject: [PATCH] platform/surface: surfacepro3_button: don't load on amd
|
||||
|
|
@ -147,7 +147,7 @@ index 242fb690dcaf..30eea54dbb47 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 397034348c39ae59b887df497f97a1c21e3a382e Mon Sep 17 00:00:00 2001
|
||||
From a8a665d668c8b626813a8fefe5c2be602fdabf31 Mon Sep 17 00:00:00 2001
|
||||
From: Hans de Goede <hdegoede@redhat.com>
|
||||
Date: Thu, 24 Feb 2022 12:02:40 +0100
|
||||
Subject: [PATCH] Input: soc_button_array - add support for Microsoft Surface 3
|
||||
|
|
@ -250,7 +250,7 @@ index 4e8944f59def..f044c731c6a9 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 84105fb580bdea48657b0a69a69613e91c5387aa Mon Sep 17 00:00:00 2001
|
||||
From 0e038f31633b889e5c4bd8b888fac74a69ac3b0f Mon Sep 17 00:00:00 2001
|
||||
From: Hans de Goede <hdegoede@redhat.com>
|
||||
Date: Thu, 24 Feb 2022 12:02:41 +0100
|
||||
Subject: [PATCH] platform/surface: Remove Surface 3 Button driver
|
||||
|
|
@ -271,7 +271,7 @@ Patchset: surface-button
|
|||
delete mode 100644 drivers/platform/surface/surface3_button.c
|
||||
|
||||
diff --git a/drivers/platform/surface/Kconfig b/drivers/platform/surface/Kconfig
|
||||
index c6c3c9bd3b57..df387ac34a79 100644
|
||||
index 3d3659b87ba4..126f940ee95a 100644
|
||||
--- a/drivers/platform/surface/Kconfig
|
||||
+++ b/drivers/platform/surface/Kconfig
|
||||
@@ -28,13 +28,6 @@ config SURFACE3_WMI
|
||||
|
|
@ -289,7 +289,7 @@ index c6c3c9bd3b57..df387ac34a79 100644
|
|||
tristate "Surface 3 battery platform operation region support"
|
||||
depends on ACPI
|
||||
diff --git a/drivers/platform/surface/Makefile b/drivers/platform/surface/Makefile
|
||||
index 9eb3a7e6382c..e4791b47f561 100644
|
||||
index 20408730f425..ea407549286c 100644
|
||||
--- a/drivers/platform/surface/Makefile
|
||||
+++ b/drivers/platform/surface/Makefile
|
||||
@@ -5,7 +5,6 @@
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From 028af0243326f55e543aec8acd2064762dd86f71 Mon Sep 17 00:00:00 2001
|
||||
From f5d22c97a860e9002ad31c8bf1c00b629c432ba7 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl>
|
||||
Date: Thu, 5 Nov 2020 13:09:45 +0100
|
||||
Subject: [PATCH] hid/multitouch: Turn off Type Cover keyboard backlight when
|
||||
|
|
@ -231,7 +231,7 @@ index 99eabfb4145b..bbfcae39f375 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 521784707c0c412e4855cbbadc56be01f78a2f69 Mon Sep 17 00:00:00 2001
|
||||
From f8ac6cc2a4f1f3020b1bcb476dc355a0e3d938ce Mon Sep 17 00:00:00 2001
|
||||
From: PJungkamp <p.jungkamp@gmail.com>
|
||||
Date: Fri, 25 Feb 2022 12:04:25 +0100
|
||||
Subject: [PATCH] hid/multitouch: Add support for surface pro type cover tablet
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From e093c33854730154848b4d604962ccbb92294f2c Mon Sep 17 00:00:00 2001
|
||||
From 00cef986201865bbfc218d4c5fc779cb877eece9 Mon Sep 17 00:00:00 2001
|
||||
From: Werner Sembach <wse@tuxedocomputers.com>
|
||||
Date: Wed, 27 Apr 2022 17:40:53 +0200
|
||||
Subject: [PATCH] ACPI: battery: Make "not-charging" the default on no charging
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From 42b9be0a9d7e155047e712274a7977e0a6eb823e Mon Sep 17 00:00:00 2001
|
||||
From 9b62ff3261ee0d1447fadafbba9243d5726708b9 Mon Sep 17 00:00:00 2001
|
||||
From: Hans de Goede <hdegoede@redhat.com>
|
||||
Date: Sun, 10 Oct 2021 20:56:57 +0200
|
||||
Subject: [PATCH] ACPI: delay enumeration of devices with a _DEP pointing to an
|
||||
|
|
@ -74,7 +74,124 @@ index c82b1bfa1c3d..2227625202aa 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From ad7593de84d5f9ecb889e201fc7dbfa6bad802f2 Mon Sep 17 00:00:00 2001
|
||||
From 1b644cf52bd707216921409e34b28367e0c033ff Mon Sep 17 00:00:00 2001
|
||||
From: zouxiaoh <xiaohong.zou@intel.com>
|
||||
Date: Fri, 25 Jun 2021 08:52:59 +0800
|
||||
Subject: [PATCH] iommu: intel-ipu: use IOMMU passthrough mode for Intel IPUs
|
||||
|
||||
Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
|
||||
The IPU driver allocates its own page table that is not mapped
|
||||
via the DMA, and thus the Intel IOMMU driver blocks access giving
|
||||
this error: DMAR: DRHD: handling fault status reg 3 DMAR:
|
||||
[DMA Read] Request device [00:05.0] PASID ffffffff
|
||||
fault addr 76406000 [fault reason 06] PTE Read access is not set
|
||||
As IPU is not an external facing device which is not risky, so use
|
||||
IOMMU passthrough mode for Intel IPUs.
|
||||
|
||||
Change-Id: I6dcccdadac308cf42e20a18e1b593381391e3e6b
|
||||
Depends-On: Iacd67578e8c6a9b9ac73285f52b4081b72fb68a6
|
||||
Tracked-On: #JIITL8-411
|
||||
Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
|
||||
Signed-off-by: zouxiaoh <xiaohong.zou@intel.com>
|
||||
Signed-off-by: Xu Chongyang <chongyang.xu@intel.com>
|
||||
Patchset: cameras
|
||||
---
|
||||
drivers/iommu/intel/iommu.c | 30 ++++++++++++++++++++++++++++++
|
||||
1 file changed, 30 insertions(+)
|
||||
|
||||
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
|
||||
index a91eed82bb39..0d16c6bf0e0b 100644
|
||||
--- a/drivers/iommu/intel/iommu.c
|
||||
+++ b/drivers/iommu/intel/iommu.c
|
||||
@@ -57,6 +57,12 @@
|
||||
#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
|
||||
#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
|
||||
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
|
||||
+#define IS_INTEL_IPU(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \
|
||||
+ ((pdev)->device == 0x9a19 || \
|
||||
+ (pdev)->device == 0x9a39 || \
|
||||
+ (pdev)->device == 0x4e19 || \
|
||||
+ (pdev)->device == 0x465d || \
|
||||
+ (pdev)->device == 0x1919))
|
||||
#define IS_IPTS(pdev) ((pdev)->vendor == PCI_VENDOR_ID_INTEL && \
|
||||
((pdev)->device == 0x9d3e))
|
||||
#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
|
||||
@@ -335,12 +341,14 @@ EXPORT_SYMBOL_GPL(intel_iommu_enabled);
|
||||
|
||||
static int dmar_map_gfx = 1;
|
||||
static int dmar_map_ipts = 1;
|
||||
+static int dmar_map_ipu = 1;
|
||||
static int intel_iommu_superpage = 1;
|
||||
static int iommu_identity_mapping;
|
||||
static int iommu_skip_te_disable;
|
||||
|
||||
#define IDENTMAP_GFX 2
|
||||
#define IDENTMAP_AZALIA 4
|
||||
+#define IDENTMAP_IPU 8
|
||||
#define IDENTMAP_IPTS 16
|
||||
|
||||
int intel_iommu_gfx_mapped;
|
||||
@@ -2992,6 +3000,9 @@ static int device_def_domain_type(struct device *dev)
|
||||
if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
|
||||
return IOMMU_DOMAIN_IDENTITY;
|
||||
|
||||
+ if ((iommu_identity_mapping & IDENTMAP_IPU) && IS_INTEL_IPU(pdev))
|
||||
+ return IOMMU_DOMAIN_IDENTITY;
|
||||
+
|
||||
if ((iommu_identity_mapping & IDENTMAP_IPTS) && IS_IPTS(pdev))
|
||||
return IOMMU_DOMAIN_IDENTITY;
|
||||
}
|
||||
@@ -3430,6 +3441,9 @@ static int __init init_dmars(void)
|
||||
if (!dmar_map_gfx)
|
||||
iommu_identity_mapping |= IDENTMAP_GFX;
|
||||
|
||||
+ if (!dmar_map_ipu)
|
||||
+ iommu_identity_mapping |= IDENTMAP_IPU;
|
||||
+
|
||||
if (!dmar_map_ipts)
|
||||
iommu_identity_mapping |= IDENTMAP_IPTS;
|
||||
|
||||
@@ -5674,6 +5688,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev)
|
||||
dmar_map_gfx = 0;
|
||||
}
|
||||
|
||||
+static void quirk_iommu_ipu(struct pci_dev *dev)
|
||||
+{
|
||||
+ if (!IS_INTEL_IPU(dev))
|
||||
+ return;
|
||||
+
|
||||
+ if (risky_device(dev))
|
||||
+ return;
|
||||
+
|
||||
+ pci_info(dev, "Passthrough IOMMU for integrated Intel IPU\n");
|
||||
+ dmar_map_ipu = 0;
|
||||
+}
|
||||
+
|
||||
static void quirk_iommu_ipts(struct pci_dev *dev)
|
||||
{
|
||||
if (!IS_IPTS(dev))
|
||||
@@ -5685,6 +5711,7 @@ static void quirk_iommu_ipts(struct pci_dev *dev)
|
||||
pci_info(dev, "Passthrough IOMMU for IPTS\n");
|
||||
dmar_map_ipts = 0;
|
||||
}
|
||||
+
|
||||
/* G4x/GM45 integrated gfx dmar support is totally busted. */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx);
|
||||
@@ -5720,6 +5747,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
|
||||
|
||||
+/* disable IPU dmar support */
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_iommu_ipu);
|
||||
+
|
||||
/* disable IPTS dmar support */
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9D3E, quirk_iommu_ipts);
|
||||
|
||||
--
|
||||
2.36.1
|
||||
|
||||
From c91db3c87b3ace9eb3b8751d16a8d81918167aa1 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Sun, 10 Oct 2021 20:57:02 +0200
|
||||
Subject: [PATCH] platform/x86: int3472: Enable I2c daisy chain
|
||||
|
|
@ -111,7 +228,7 @@ index 22f61b47f9e5..e1de1ff40bba 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 910b0dc55c6a5a631b0308a1561c65398ad6421a Mon Sep 17 00:00:00 2001
|
||||
From 87e937e41f4b0ee24743f8d23b873e38a9b4c8ff Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Thu, 28 Oct 2021 21:55:16 +0100
|
||||
Subject: [PATCH] media: i2c: Add driver for DW9719 VCM
|
||||
|
|
@ -617,7 +734,7 @@ index 000000000000..8451c75b696b
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 77f2ff5654488eadf3725644e8f1c08861d3bad4 Mon Sep 17 00:00:00 2001
|
||||
From b3f48443b9e4d4fd4d62e157a1a9fc5c5a3172c1 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Mon, 13 Dec 2021 22:38:17 +0000
|
||||
Subject: [PATCH] media: entity: Skip non-data links in graph iteration
|
||||
|
|
@ -652,7 +769,7 @@ index b411f9796191..d0563ee4b28b 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 3399c718f545d0dc91f12163df6a7946c9c1d4ed Mon Sep 17 00:00:00 2001
|
||||
From 0016f1cc163433a701cfb3bf2724b2498977aec1 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Mon, 13 Dec 2021 22:53:09 +0000
|
||||
Subject: [PATCH] media: media.h: Add new media link type
|
||||
|
|
@ -736,7 +853,7 @@ index 200fa8462b90..afbae7213d35 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 511e79d5ba0200de56f32be6cf5bebd368071fd1 Mon Sep 17 00:00:00 2001
|
||||
From 8263f61bdcef252cf1f847e96ac70a3f237a176c Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Mon, 13 Dec 2021 22:36:31 +0000
|
||||
Subject: [PATCH] media: entity: Add link_type_name() helper
|
||||
|
|
@ -791,7 +908,7 @@ index d0563ee4b28b..1a7d0a4fb9e8 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From cf0742d09ede8e75f69bd6bcec3b8a98856ac4c5 Mon Sep 17 00:00:00 2001
|
||||
From 1d5ac8ff430953b6e4a21145444bb4784b62ce61 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Mon, 13 Dec 2021 22:54:10 +0000
|
||||
Subject: [PATCH] media: entity: Add support for ancillary links
|
||||
|
|
@ -868,7 +985,7 @@ index fea489f03d57..2a58defc4886 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From d75aabdabf67a09d6ffdc1f975f28e30dae2212f Mon Sep 17 00:00:00 2001
|
||||
From d73c5be1644e13387421d110a777a4ca2a89b180 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Fri, 26 Nov 2021 22:55:50 +0000
|
||||
Subject: [PATCH] media: v4l2-async: Create links during
|
||||
|
|
@ -941,7 +1058,7 @@ index 0404267f1ae4..436bd6900fd8 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From 22617184a837d41b3a942caa9bc0d0d715152a46 Mon Sep 17 00:00:00 2001
|
||||
From 359b0ab317c47c26eb3827148900c2fd37de5386 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Scally <djrscally@gmail.com>
|
||||
Date: Wed, 4 May 2022 23:21:45 +0100
|
||||
Subject: [PATCH] media: ipu3-cio2: Move functionality from .complete() to
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
From 2e2c39b2ec3d9ed520d5d956a8e3904574129ac3 Mon Sep 17 00:00:00 2001
|
||||
From 06d469f4087d37327bb5e73f86252a75dc154e8d Mon Sep 17 00:00:00 2001
|
||||
From: Sachi King <nakato@nakato.io>
|
||||
Date: Sat, 29 May 2021 17:47:38 +1000
|
||||
Subject: [PATCH] ACPI: Add quirk for Surface Laptop 4 AMD missing irq 7
|
||||
|
|
@ -65,7 +65,7 @@ index 0d01e7f5078c..2b06cf5f2b1f 100644
|
|||
--
|
||||
2.36.1
|
||||
|
||||
From fbaa262eea4001d779f9bec1eb252152da2c9280 Mon Sep 17 00:00:00 2001
|
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From ea19767e72dac9648cf5cb7a8a7005b61a070327 Mon Sep 17 00:00:00 2001
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From: Maximilian Luz <luzmaximilian@gmail.com>
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Date: Thu, 3 Jun 2021 14:04:26 +0200
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Subject: [PATCH] ACPI: Add AMD 13" Surface Laptop 4 model to irq 7 override
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