updating to mainline 4.12.8
This commit is contained in:
Jake Day
parent
87cc090a19
commit
198e84c4f7
2
Makefile
2
Makefile
|
|
@ -1,6 +1,6 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 12
|
||||
SUBLEVEL = 6
|
||||
SUBLEVEL = 8
|
||||
EXTRAVERSION =
|
||||
NAME = Fearless Coyote
|
||||
|
||||
|
|
|
|||
|
|
@ -147,23 +147,12 @@
|
|||
* Find irq with highest priority
|
||||
*/
|
||||
# open coded PTR_LA t1, cpu_mask_nr_tbl
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
|
||||
# open coded la t1, cpu_mask_nr_tbl
|
||||
lui t1, %hi(cpu_mask_nr_tbl)
|
||||
addiu t1, %lo(cpu_mask_nr_tbl)
|
||||
|
||||
#endif
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
# open coded dla t1, cpu_mask_nr_tbl
|
||||
.set push
|
||||
.set noat
|
||||
lui t1, %highest(cpu_mask_nr_tbl)
|
||||
lui AT, %hi(cpu_mask_nr_tbl)
|
||||
daddiu t1, t1, %higher(cpu_mask_nr_tbl)
|
||||
daddiu AT, AT, %lo(cpu_mask_nr_tbl)
|
||||
dsll t1, 32
|
||||
daddu t1, t1, AT
|
||||
.set pop
|
||||
#else
|
||||
#error GCC `-msym32' option required for 64-bit DECstation builds
|
||||
#endif
|
||||
1: lw t2,(t1)
|
||||
nop
|
||||
|
|
@ -214,23 +203,12 @@
|
|||
* Find irq with highest priority
|
||||
*/
|
||||
# open coded PTR_LA t1,asic_mask_nr_tbl
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
|
||||
# open coded la t1, asic_mask_nr_tbl
|
||||
lui t1, %hi(asic_mask_nr_tbl)
|
||||
addiu t1, %lo(asic_mask_nr_tbl)
|
||||
|
||||
#endif
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
# open coded dla t1, asic_mask_nr_tbl
|
||||
.set push
|
||||
.set noat
|
||||
lui t1, %highest(asic_mask_nr_tbl)
|
||||
lui AT, %hi(asic_mask_nr_tbl)
|
||||
daddiu t1, t1, %higher(asic_mask_nr_tbl)
|
||||
daddiu AT, AT, %lo(asic_mask_nr_tbl)
|
||||
dsll t1, 32
|
||||
daddu t1, t1, AT
|
||||
.set pop
|
||||
#else
|
||||
#error GCC `-msym32' option required for 64-bit DECstation builds
|
||||
#endif
|
||||
2: lw t2,(t1)
|
||||
nop
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@
|
|||
#ifndef _ASM_CACHE_H
|
||||
#define _ASM_CACHE_H
|
||||
|
||||
#include <kmalloc.h>
|
||||
|
||||
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,10 @@
|
|||
#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
|
||||
#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
|
||||
#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
|
||||
#define CVMX_L2C_ERR_TDTX(block_id) \
|
||||
(CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
|
||||
#define CVMX_L2C_ERR_TTGX(block_id) \
|
||||
(CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
|
||||
#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
|
||||
#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
|
||||
#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
|
||||
|
|
@ -66,9 +70,40 @@
|
|||
((offset) & 1) * 8)
|
||||
#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \
|
||||
((offset) & 31) * 8)
|
||||
#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
|
||||
|
||||
|
||||
union cvmx_l2c_err_tdtx {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2c_err_tdtx_s {
|
||||
__BITFIELD_FIELD(uint64_t dbe:1,
|
||||
__BITFIELD_FIELD(uint64_t sbe:1,
|
||||
__BITFIELD_FIELD(uint64_t vdbe:1,
|
||||
__BITFIELD_FIELD(uint64_t vsbe:1,
|
||||
__BITFIELD_FIELD(uint64_t syn:10,
|
||||
__BITFIELD_FIELD(uint64_t reserved_22_49:28,
|
||||
__BITFIELD_FIELD(uint64_t wayidx:18,
|
||||
__BITFIELD_FIELD(uint64_t reserved_2_3:2,
|
||||
__BITFIELD_FIELD(uint64_t type:2,
|
||||
;)))))))))
|
||||
} s;
|
||||
};
|
||||
|
||||
union cvmx_l2c_err_ttgx {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2c_err_ttgx_s {
|
||||
__BITFIELD_FIELD(uint64_t dbe:1,
|
||||
__BITFIELD_FIELD(uint64_t sbe:1,
|
||||
__BITFIELD_FIELD(uint64_t noway:1,
|
||||
__BITFIELD_FIELD(uint64_t reserved_56_60:5,
|
||||
__BITFIELD_FIELD(uint64_t syn:6,
|
||||
__BITFIELD_FIELD(uint64_t reserved_22_49:28,
|
||||
__BITFIELD_FIELD(uint64_t wayidx:15,
|
||||
__BITFIELD_FIELD(uint64_t reserved_2_6:5,
|
||||
__BITFIELD_FIELD(uint64_t type:2,
|
||||
;)))))))))
|
||||
} s;
|
||||
};
|
||||
|
||||
union cvmx_l2c_cfg {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2c_cfg_s {
|
||||
|
|
|
|||
60
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
Normal file
60
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/***********************license start***************
|
||||
* Author: Cavium Networks
|
||||
*
|
||||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2017 Cavium, Inc.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful, but
|
||||
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
|
||||
* NONINFRINGEMENT. See the GNU General Public License for more
|
||||
* details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this file; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* or visit http://www.gnu.org/licenses/.
|
||||
*
|
||||
* This file may also be available under a different license from Cavium.
|
||||
* Contact Cavium Networks for more information
|
||||
***********************license end**************************************/
|
||||
|
||||
#ifndef __CVMX_L2D_DEFS_H__
|
||||
#define __CVMX_L2D_DEFS_H__
|
||||
|
||||
#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
|
||||
#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
|
||||
|
||||
|
||||
union cvmx_l2d_err {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2d_err_s {
|
||||
__BITFIELD_FIELD(uint64_t reserved_6_63:58,
|
||||
__BITFIELD_FIELD(uint64_t bmhclsel:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;)))))))
|
||||
} s;
|
||||
};
|
||||
|
||||
union cvmx_l2d_fus3 {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2d_fus3_s {
|
||||
__BITFIELD_FIELD(uint64_t reserved_40_63:24,
|
||||
__BITFIELD_FIELD(uint64_t ema_ctl:3,
|
||||
__BITFIELD_FIELD(uint64_t reserved_34_36:3,
|
||||
__BITFIELD_FIELD(uint64_t q3fus:34,
|
||||
;))))
|
||||
} s;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -62,6 +62,7 @@ enum cvmx_mips_space {
|
|||
#include <asm/octeon/cvmx-iob-defs.h>
|
||||
#include <asm/octeon/cvmx-ipd-defs.h>
|
||||
#include <asm/octeon/cvmx-l2c-defs.h>
|
||||
#include <asm/octeon/cvmx-l2d-defs.h>
|
||||
#include <asm/octeon/cvmx-l2t-defs.h>
|
||||
#include <asm/octeon/cvmx-led-defs.h>
|
||||
#include <asm/octeon/cvmx-mio-defs.h>
|
||||
|
|
|
|||
|
|
@ -335,6 +335,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
maj = ((pvr >> 8) & 0xFF) - 1;
|
||||
min = pvr & 0xFF;
|
||||
break;
|
||||
case 0x004e: /* POWER9 bits 12-15 give chip type */
|
||||
maj = (pvr >> 8) & 0x0F;
|
||||
min = pvr & 0xFF;
|
||||
break;
|
||||
default:
|
||||
maj = (pvr >> 8) & 0xFF;
|
||||
min = pvr & 0xFF;
|
||||
|
|
|
|||
|
|
@ -1253,7 +1253,8 @@ static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
|
|||
insn_count = bpf_jit_insn(jit, fp, i);
|
||||
if (insn_count < 0)
|
||||
return -1;
|
||||
jit->addrs[i + 1] = jit->prg; /* Next instruction address */
|
||||
/* Next instruction address */
|
||||
jit->addrs[i + insn_count] = jit->prg;
|
||||
}
|
||||
bpf_jit_epilogue(jit);
|
||||
|
||||
|
|
|
|||
|
|
@ -94,13 +94,11 @@ unsigned long __sync_fetch_and_or_4(unsigned long *p, unsigned long v)
|
|||
}
|
||||
EXPORT_SYMBOL(__sync_fetch_and_or_4);
|
||||
|
||||
#ifdef CONFIG_NET
|
||||
/*
|
||||
* Networking support
|
||||
*/
|
||||
EXPORT_SYMBOL(csum_partial);
|
||||
EXPORT_SYMBOL(csum_partial_copy_generic);
|
||||
#endif /* CONFIG_NET */
|
||||
|
||||
/*
|
||||
* Architecture-specific symbols
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@ void clear_user_highpage(struct page *page, unsigned long vaddr)
|
|||
clear_page_alias(kvaddr, paddr);
|
||||
preempt_enable();
|
||||
}
|
||||
EXPORT_SYMBOL(clear_user_highpage);
|
||||
|
||||
void copy_user_highpage(struct page *dst, struct page *src,
|
||||
unsigned long vaddr, struct vm_area_struct *vma)
|
||||
|
|
@ -119,10 +120,7 @@ void copy_user_highpage(struct page *dst, struct page *src,
|
|||
copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
|
||||
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
|
||||
EXPORT_SYMBOL(copy_user_highpage);
|
||||
|
||||
/*
|
||||
* Any time the kernel writes to a user page cache page, or it is about to
|
||||
|
|
@ -176,7 +174,7 @@ void flush_dcache_page(struct page *page)
|
|||
|
||||
/* There shouldn't be an entry in the cache for this page anymore. */
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(flush_dcache_page);
|
||||
|
||||
/*
|
||||
* For now, flush the whole cache. FIXME??
|
||||
|
|
@ -188,6 +186,7 @@ void local_flush_cache_range(struct vm_area_struct *vma,
|
|||
__flush_invalidate_dcache_all();
|
||||
__invalidate_icache_all();
|
||||
}
|
||||
EXPORT_SYMBOL(local_flush_cache_range);
|
||||
|
||||
/*
|
||||
* Remove any entry in the cache for this page.
|
||||
|
|
@ -207,8 +206,9 @@ void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
|
|||
__flush_invalidate_dcache_page_alias(virt, phys);
|
||||
__invalidate_icache_page_alias(virt, phys);
|
||||
}
|
||||
EXPORT_SYMBOL(local_flush_cache_page);
|
||||
|
||||
#endif
|
||||
#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
|
||||
|
||||
void
|
||||
update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
|
||||
|
|
@ -225,7 +225,7 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
|
|||
|
||||
flush_tlb_page(vma, addr);
|
||||
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
|
||||
|
||||
if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
|
||||
unsigned long phys = page_to_phys(page);
|
||||
|
|
@ -256,7 +256,7 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
|
|||
* flush_dcache_page() on the page.
|
||||
*/
|
||||
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
|
||||
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
|
||||
|
||||
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long vaddr, void *dst, const void *src,
|
||||
|
|
|
|||
|
|
@ -620,8 +620,8 @@ EXPORT_SYMBOL(blk_mq_kick_requeue_list);
|
|||
void blk_mq_delay_kick_requeue_list(struct request_queue *q,
|
||||
unsigned long msecs)
|
||||
{
|
||||
kblockd_schedule_delayed_work(&q->requeue_work,
|
||||
msecs_to_jiffies(msecs));
|
||||
kblockd_mod_delayed_work_on(WORK_CPU_UNBOUND, &q->requeue_work,
|
||||
msecs_to_jiffies(msecs));
|
||||
}
|
||||
EXPORT_SYMBOL(blk_mq_delay_kick_requeue_list);
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
#include <linux/syscore_ops.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/security.h>
|
||||
#include <linux/swait.h>
|
||||
|
||||
#include <generated/utsrelease.h>
|
||||
|
||||
|
|
@ -112,13 +111,13 @@ static inline long firmware_loading_timeout(void)
|
|||
* state of the firmware loading.
|
||||
*/
|
||||
struct fw_state {
|
||||
struct swait_queue_head wq;
|
||||
struct completion completion;
|
||||
enum fw_status status;
|
||||
};
|
||||
|
||||
static void fw_state_init(struct fw_state *fw_st)
|
||||
{
|
||||
init_swait_queue_head(&fw_st->wq);
|
||||
init_completion(&fw_st->completion);
|
||||
fw_st->status = FW_STATUS_UNKNOWN;
|
||||
}
|
||||
|
||||
|
|
@ -131,9 +130,7 @@ static int __fw_state_wait_common(struct fw_state *fw_st, long timeout)
|
|||
{
|
||||
long ret;
|
||||
|
||||
ret = swait_event_interruptible_timeout(fw_st->wq,
|
||||
__fw_state_is_done(READ_ONCE(fw_st->status)),
|
||||
timeout);
|
||||
ret = wait_for_completion_killable_timeout(&fw_st->completion, timeout);
|
||||
if (ret != 0 && fw_st->status == FW_STATUS_ABORTED)
|
||||
return -ENOENT;
|
||||
if (!ret)
|
||||
|
|
@ -148,35 +145,34 @@ static void __fw_state_set(struct fw_state *fw_st,
|
|||
WRITE_ONCE(fw_st->status, status);
|
||||
|
||||
if (status == FW_STATUS_DONE || status == FW_STATUS_ABORTED)
|
||||
swake_up(&fw_st->wq);
|
||||
complete_all(&fw_st->completion);
|
||||
}
|
||||
|
||||
#define fw_state_start(fw_st) \
|
||||
__fw_state_set(fw_st, FW_STATUS_LOADING)
|
||||
#define fw_state_done(fw_st) \
|
||||
__fw_state_set(fw_st, FW_STATUS_DONE)
|
||||
#define fw_state_aborted(fw_st) \
|
||||
__fw_state_set(fw_st, FW_STATUS_ABORTED)
|
||||
#define fw_state_wait(fw_st) \
|
||||
__fw_state_wait_common(fw_st, MAX_SCHEDULE_TIMEOUT)
|
||||
|
||||
#ifndef CONFIG_FW_LOADER_USER_HELPER
|
||||
|
||||
#define fw_state_is_aborted(fw_st) false
|
||||
|
||||
#else /* CONFIG_FW_LOADER_USER_HELPER */
|
||||
|
||||
static int __fw_state_check(struct fw_state *fw_st, enum fw_status status)
|
||||
{
|
||||
return fw_st->status == status;
|
||||
}
|
||||
|
||||
#define fw_state_is_aborted(fw_st) \
|
||||
__fw_state_check(fw_st, FW_STATUS_ABORTED)
|
||||
|
||||
#ifdef CONFIG_FW_LOADER_USER_HELPER
|
||||
|
||||
#define fw_state_aborted(fw_st) \
|
||||
__fw_state_set(fw_st, FW_STATUS_ABORTED)
|
||||
#define fw_state_is_done(fw_st) \
|
||||
__fw_state_check(fw_st, FW_STATUS_DONE)
|
||||
#define fw_state_is_loading(fw_st) \
|
||||
__fw_state_check(fw_st, FW_STATUS_LOADING)
|
||||
#define fw_state_is_aborted(fw_st) \
|
||||
__fw_state_check(fw_st, FW_STATUS_ABORTED)
|
||||
#define fw_state_wait_timeout(fw_st, timeout) \
|
||||
__fw_state_wait_common(fw_st, timeout)
|
||||
|
||||
|
|
@ -1163,6 +1159,28 @@ static int assign_firmware_buf(struct firmware *fw, struct device *device,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Batched requests need only one wake, we need to do this step last due to the
|
||||
* fallback mechanism. The buf is protected with kref_get(), and it won't be
|
||||
* released until the last user calls release_firmware().
|
||||
*
|
||||
* Failed batched requests are possible as well, in such cases we just share
|
||||
* the struct firmware_buf and won't release it until all requests are woken
|
||||
* and have gone through this same path.
|
||||
*/
|
||||
static void fw_abort_batch_reqs(struct firmware *fw)
|
||||
{
|
||||
struct firmware_buf *buf;
|
||||
|
||||
/* Loaded directly? */
|
||||
if (!fw || !fw->priv)
|
||||
return;
|
||||
|
||||
buf = fw->priv;
|
||||
if (!fw_state_is_aborted(&buf->fw_st))
|
||||
fw_state_aborted(&buf->fw_st);
|
||||
}
|
||||
|
||||
/* called from request_firmware() and request_firmware_work_func() */
|
||||
static int
|
||||
_request_firmware(const struct firmware **firmware_p, const char *name,
|
||||
|
|
@ -1224,6 +1242,7 @@ _request_firmware(const struct firmware **firmware_p, const char *name,
|
|||
|
||||
out:
|
||||
if (ret < 0) {
|
||||
fw_abort_batch_reqs(fw);
|
||||
release_firmware(fw);
|
||||
fw = NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1255,7 +1255,7 @@ static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
|
|||
|
||||
/* port@2 is the output port */
|
||||
ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
|
||||
if (ret)
|
||||
if (ret && ret != -ENODEV)
|
||||
return ret;
|
||||
|
||||
/* Shut down GPIO is optional */
|
||||
|
|
|
|||
|
|
@ -270,8 +270,8 @@ static int submit_reloc(struct etnaviv_gem_submit *submit, void *stream,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (r->reloc_offset >= bo->obj->base.size - sizeof(*ptr)) {
|
||||
DRM_ERROR("relocation %u outside object", i);
|
||||
if (r->reloc_offset > bo->obj->base.size - sizeof(*ptr)) {
|
||||
DRM_ERROR("relocation %u outside object\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -398,6 +398,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
|
|||
}
|
||||
|
||||
/* Program the max register to clamp values > 1.0. */
|
||||
i = lut_size - 1;
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
|
||||
drm_color_lut_extract(lut[i].red, 16));
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
|
||||
|
|
|
|||
|
|
@ -254,6 +254,9 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
acpi_speed = i2c_acpi_find_bus_speed(&pdev->dev);
|
||||
/* Some broken DSTDs use 1MiHz instead of 1MHz */
|
||||
if (acpi_speed == 1048576)
|
||||
acpi_speed = 1000000;
|
||||
/*
|
||||
* Find bus speed from the "clock-frequency" device property, ACPI
|
||||
* or by using fast mode if neither is set.
|
||||
|
|
|
|||
|
|
@ -193,7 +193,6 @@ struct bmc150_accel_data {
|
|||
struct regmap *regmap;
|
||||
int irq;
|
||||
struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
|
||||
atomic_t active_intr;
|
||||
struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
|
||||
struct mutex mutex;
|
||||
u8 fifo_mode, watermark;
|
||||
|
|
@ -493,11 +492,6 @@ static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
|
|||
goto out_fix_power_state;
|
||||
}
|
||||
|
||||
if (state)
|
||||
atomic_inc(&data->active_intr);
|
||||
else
|
||||
atomic_dec(&data->active_intr);
|
||||
|
||||
return 0;
|
||||
|
||||
out_fix_power_state:
|
||||
|
|
@ -1710,8 +1704,7 @@ static int bmc150_accel_resume(struct device *dev)
|
|||
struct bmc150_accel_data *data = iio_priv(indio_dev);
|
||||
|
||||
mutex_lock(&data->mutex);
|
||||
if (atomic_read(&data->active_intr))
|
||||
bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
|
||||
bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
|
||||
bmc150_accel_fifo_set_mode(data);
|
||||
mutex_unlock(&data->mutex);
|
||||
|
||||
|
|
|
|||
|
|
@ -166,6 +166,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_ihl = 0x02,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x23,
|
||||
.value = BIT(0),
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
@ -234,6 +238,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_od = 0x40,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x23,
|
||||
.value = BIT(0),
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
@ -316,6 +324,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.en_mask = 0x08,
|
||||
},
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x24,
|
||||
.value = BIT(0),
|
||||
},
|
||||
.multi_read_bit = false,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
@ -379,6 +391,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_int1 = 0x04,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x21,
|
||||
.value = BIT(1),
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.bootime = 2, /* guess */
|
||||
},
|
||||
|
|
@ -437,6 +453,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_od = 0x40,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x21,
|
||||
.value = BIT(7),
|
||||
},
|
||||
.multi_read_bit = false,
|
||||
.bootime = 2, /* guess */
|
||||
},
|
||||
|
|
@ -499,6 +519,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.addr_ihl = 0x22,
|
||||
.mask_ihl = 0x80,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x23,
|
||||
.value = BIT(0),
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
@ -547,6 +571,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_int1 = 0x04,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x21,
|
||||
.value = BIT(1),
|
||||
},
|
||||
.multi_read_bit = false,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
@ -614,6 +642,10 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
|
|||
.mask_ihl = 0x02,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.sim = {
|
||||
.addr = 0x23,
|
||||
.value = BIT(0),
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.bootime = 2,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include <linux/iio/iio.h>
|
||||
#include <linux/iio/driver.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#define ASPEED_RESOLUTION_BITS 10
|
||||
#define ASPEED_CLOCKS_PER_SAMPLE 12
|
||||
|
|
@ -38,11 +39,17 @@
|
|||
|
||||
#define ASPEED_ENGINE_ENABLE BIT(0)
|
||||
|
||||
#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
|
||||
|
||||
#define ASPEED_ADC_INIT_POLLING_TIME 500
|
||||
#define ASPEED_ADC_INIT_TIMEOUT 500000
|
||||
|
||||
struct aspeed_adc_model_data {
|
||||
const char *model_name;
|
||||
unsigned int min_sampling_rate; // Hz
|
||||
unsigned int max_sampling_rate; // Hz
|
||||
unsigned int vref_voltage; // mV
|
||||
bool wait_init_sequence;
|
||||
};
|
||||
|
||||
struct aspeed_adc_data {
|
||||
|
|
@ -211,6 +218,24 @@ static int aspeed_adc_probe(struct platform_device *pdev)
|
|||
goto scaler_error;
|
||||
}
|
||||
|
||||
model_data = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
if (model_data->wait_init_sequence) {
|
||||
/* Enable engine in normal mode. */
|
||||
writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
|
||||
data->base + ASPEED_REG_ENGINE_CONTROL);
|
||||
|
||||
/* Wait for initial sequence complete. */
|
||||
ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
|
||||
adc_engine_control_reg_val,
|
||||
adc_engine_control_reg_val &
|
||||
ASPEED_ADC_CTRL_INIT_RDY,
|
||||
ASPEED_ADC_INIT_POLLING_TIME,
|
||||
ASPEED_ADC_INIT_TIMEOUT);
|
||||
if (ret)
|
||||
goto scaler_error;
|
||||
}
|
||||
|
||||
/* Start all channels in normal mode. */
|
||||
clk_prepare_enable(data->clk_scaler->clk);
|
||||
adc_engine_control_reg_val = GENMASK(31, 16) |
|
||||
|
|
@ -270,6 +295,7 @@ static const struct aspeed_adc_model_data ast2500_model_data = {
|
|||
.vref_voltage = 1800, // mV
|
||||
.min_sampling_rate = 1,
|
||||
.max_sampling_rate = 1000000,
|
||||
.wait_init_sequence = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id aspeed_adc_matches[] = {
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
#include <linux/iio/driver.h>
|
||||
|
||||
#define AXP288_ADC_EN_MASK 0xF1
|
||||
#define AXP288_ADC_TS_PIN_GPADC 0xF2
|
||||
#define AXP288_ADC_TS_PIN_ON 0xF3
|
||||
|
||||
enum axp288_adc_id {
|
||||
AXP288_ADC_TS,
|
||||
|
|
@ -121,6 +123,16 @@ static int axp288_adc_read_channel(int *val, unsigned long address,
|
|||
return IIO_VAL_INT;
|
||||
}
|
||||
|
||||
static int axp288_adc_set_ts(struct regmap *regmap, unsigned int mode,
|
||||
unsigned long address)
|
||||
{
|
||||
/* channels other than GPADC do not need to switch TS pin */
|
||||
if (address != AXP288_GP_ADC_H)
|
||||
return 0;
|
||||
|
||||
return regmap_write(regmap, AXP288_ADC_TS_PIN_CTRL, mode);
|
||||
}
|
||||
|
||||
static int axp288_adc_read_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int *val, int *val2, long mask)
|
||||
|
|
@ -131,7 +143,16 @@ static int axp288_adc_read_raw(struct iio_dev *indio_dev,
|
|||
mutex_lock(&indio_dev->mlock);
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
if (axp288_adc_set_ts(info->regmap, AXP288_ADC_TS_PIN_GPADC,
|
||||
chan->address)) {
|
||||
dev_err(&indio_dev->dev, "GPADC mode\n");
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
ret = axp288_adc_read_channel(val, chan->address, info->regmap);
|
||||
if (axp288_adc_set_ts(info->regmap, AXP288_ADC_TS_PIN_ON,
|
||||
chan->address))
|
||||
dev_err(&indio_dev->dev, "TS pin restore\n");
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
|
|
@ -141,6 +162,15 @@ static int axp288_adc_read_raw(struct iio_dev *indio_dev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int axp288_adc_set_state(struct regmap *regmap)
|
||||
{
|
||||
/* ADC should be always enabled for internal FG to function */
|
||||
if (regmap_write(regmap, AXP288_ADC_TS_PIN_CTRL, AXP288_ADC_TS_PIN_ON))
|
||||
return -EIO;
|
||||
|
||||
return regmap_write(regmap, AXP20X_ADC_EN1, AXP288_ADC_EN_MASK);
|
||||
}
|
||||
|
||||
static const struct iio_info axp288_adc_iio_info = {
|
||||
.read_raw = &axp288_adc_read_raw,
|
||||
.driver_module = THIS_MODULE,
|
||||
|
|
@ -169,7 +199,7 @@ static int axp288_adc_probe(struct platform_device *pdev)
|
|||
* Set ADC to enabled state at all time, including system suspend.
|
||||
* otherwise internal fuel gauge functionality may be affected.
|
||||
*/
|
||||
ret = regmap_write(info->regmap, AXP20X_ADC_EN1, AXP288_ADC_EN_MASK);
|
||||
ret = axp288_adc_set_state(axp20x->regmap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to enable ADC device\n");
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
#define VF610_ADC_ADSTS_MASK 0x300
|
||||
#define VF610_ADC_ADLPC_EN 0x80
|
||||
#define VF610_ADC_ADHSC_EN 0x400
|
||||
#define VF610_ADC_REFSEL_VALT 0x100
|
||||
#define VF610_ADC_REFSEL_VALT 0x800
|
||||
#define VF610_ADC_REFSEL_VBG 0x1000
|
||||
#define VF610_ADC_ADTRG_HARD 0x2000
|
||||
#define VF610_ADC_AVGS_8 0x4000
|
||||
|
|
|
|||
|
|
@ -550,6 +550,31 @@ out:
|
|||
}
|
||||
EXPORT_SYMBOL(st_sensors_read_info_raw);
|
||||
|
||||
static int st_sensors_init_interface_mode(struct iio_dev *indio_dev,
|
||||
const struct st_sensor_settings *sensor_settings)
|
||||
{
|
||||
struct st_sensor_data *sdata = iio_priv(indio_dev);
|
||||
struct device_node *np = sdata->dev->of_node;
|
||||
struct st_sensors_platform_data *pdata;
|
||||
|
||||
pdata = (struct st_sensors_platform_data *)sdata->dev->platform_data;
|
||||
if (((np && of_property_read_bool(np, "spi-3wire")) ||
|
||||
(pdata && pdata->spi_3wire)) && sensor_settings->sim.addr) {
|
||||
int err;
|
||||
|
||||
err = sdata->tf->write_byte(&sdata->tb, sdata->dev,
|
||||
sensor_settings->sim.addr,
|
||||
sensor_settings->sim.value);
|
||||
if (err < 0) {
|
||||
dev_err(&indio_dev->dev,
|
||||
"failed to init interface mode\n");
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int st_sensors_check_device_support(struct iio_dev *indio_dev,
|
||||
int num_sensors_list,
|
||||
const struct st_sensor_settings *sensor_settings)
|
||||
|
|
@ -574,6 +599,10 @@ int st_sensors_check_device_support(struct iio_dev *indio_dev,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
err = st_sensors_init_interface_mode(indio_dev, &sensor_settings[i]);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
if (sensor_settings[i].wai_addr) {
|
||||
err = sdata->tf->read_byte(&sdata->tb, sdata->dev,
|
||||
sensor_settings[i].wai_addr, &wai);
|
||||
|
|
|
|||
|
|
@ -626,7 +626,7 @@ static irqreturn_t tsl2563_event_handler(int irq, void *private)
|
|||
struct tsl2563_chip *chip = iio_priv(dev_info);
|
||||
|
||||
iio_push_event(dev_info,
|
||||
IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
|
||||
IIO_UNMOD_EVENT_CODE(IIO_INTENSITY,
|
||||
0,
|
||||
IIO_EV_TYPE_THRESH,
|
||||
IIO_EV_DIR_EITHER),
|
||||
|
|
|
|||
|
|
@ -456,7 +456,7 @@ static const struct st_sensor_settings st_press_sensors_settings[] = {
|
|||
.mask_od = 0x40,
|
||||
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
|
||||
},
|
||||
.multi_read_bit = true,
|
||||
.multi_read_bit = false,
|
||||
.bootime = 2,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1288,7 +1288,7 @@ out_err:
|
|||
static int mmc_select_hs400es(struct mmc_card *card)
|
||||
{
|
||||
struct mmc_host *host = card->host;
|
||||
int err = 0;
|
||||
int err = -EINVAL;
|
||||
u8 val;
|
||||
|
||||
if (!(host->caps & MMC_CAP_8_BIT_DATA)) {
|
||||
|
|
|
|||
|
|
@ -945,6 +945,7 @@ struct atmel_pmecc *devm_atmel_pmecc_get(struct device *userdev)
|
|||
*/
|
||||
struct platform_device *pdev = to_platform_device(userdev);
|
||||
const struct atmel_pmecc_caps *caps;
|
||||
const struct of_device_id *match;
|
||||
|
||||
/* No PMECC engine available. */
|
||||
if (!of_property_read_bool(userdev->of_node,
|
||||
|
|
@ -953,21 +954,11 @@ struct atmel_pmecc *devm_atmel_pmecc_get(struct device *userdev)
|
|||
|
||||
caps = &at91sam9g45_caps;
|
||||
|
||||
/*
|
||||
* Try to find the NFC subnode and extract the associated caps
|
||||
* from there.
|
||||
*/
|
||||
np = of_find_compatible_node(userdev->of_node, NULL,
|
||||
"atmel,sama5d3-nfc");
|
||||
if (np) {
|
||||
const struct of_device_id *match;
|
||||
|
||||
match = of_match_node(atmel_pmecc_legacy_match, np);
|
||||
if (match && match->data)
|
||||
caps = match->data;
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
/* Find the caps associated to the NAND dev node. */
|
||||
match = of_match_node(atmel_pmecc_legacy_match,
|
||||
userdev->of_node);
|
||||
if (match && match->data)
|
||||
caps = match->data;
|
||||
|
||||
pmecc = atmel_pmecc_create(pdev, caps, 1, 2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,8 +65,14 @@ static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
|
|||
|
||||
if (!section) {
|
||||
oobregion->offset = 0;
|
||||
oobregion->length = 4;
|
||||
if (mtd->oobsize == 16)
|
||||
oobregion->length = 4;
|
||||
else
|
||||
oobregion->length = 3;
|
||||
} else {
|
||||
if (mtd->oobsize == 8)
|
||||
return -ERANGE;
|
||||
|
||||
oobregion->offset = 6;
|
||||
oobregion->length = ecc->total - 4;
|
||||
}
|
||||
|
|
@ -1102,7 +1108,9 @@ static int nand_setup_data_interface(struct nand_chip *chip)
|
|||
* Ensure the timing mode has been changed on the chip side
|
||||
* before changing timings on the controller side.
|
||||
*/
|
||||
if (chip->onfi_version) {
|
||||
if (chip->onfi_version &&
|
||||
(le16_to_cpu(chip->onfi_params.opt_cmd) &
|
||||
ONFI_OPT_CMD_SET_GET_FEATURES)) {
|
||||
u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
|
||||
chip->onfi_timing_mode_default,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -311,9 +311,9 @@ int onfi_init_data_interface(struct nand_chip *chip,
|
|||
struct nand_sdr_timings *timings = &iface->timings.sdr;
|
||||
|
||||
/* microseconds -> picoseconds */
|
||||
timings->tPROG_max = 1000000UL * le16_to_cpu(params->t_prog);
|
||||
timings->tBERS_max = 1000000UL * le16_to_cpu(params->t_bers);
|
||||
timings->tR_max = 1000000UL * le16_to_cpu(params->t_r);
|
||||
timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog);
|
||||
timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers);
|
||||
timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r);
|
||||
|
||||
/* nanoseconds -> picoseconds */
|
||||
timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs);
|
||||
|
|
|
|||
|
|
@ -572,16 +572,21 @@ static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
|
|||
* header, the HW adds it. To address that, we are subtracting the pseudo
|
||||
* header checksum from the checksum value provided by the HW.
|
||||
*/
|
||||
static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
|
||||
struct iphdr *iph)
|
||||
static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
|
||||
struct iphdr *iph)
|
||||
{
|
||||
__u16 length_for_csum = 0;
|
||||
__wsum csum_pseudo_header = 0;
|
||||
__u8 ipproto = iph->protocol;
|
||||
|
||||
if (unlikely(ipproto == IPPROTO_SCTP))
|
||||
return -1;
|
||||
|
||||
length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
|
||||
csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
|
||||
length_for_csum, iph->protocol, 0);
|
||||
length_for_csum, ipproto, 0);
|
||||
skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
|
|
@ -592,17 +597,20 @@ static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
|
|||
static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
|
||||
struct ipv6hdr *ipv6h)
|
||||
{
|
||||
__u8 nexthdr = ipv6h->nexthdr;
|
||||
__wsum csum_pseudo_hdr = 0;
|
||||
|
||||
if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
|
||||
ipv6h->nexthdr == IPPROTO_HOPOPTS))
|
||||
if (unlikely(nexthdr == IPPROTO_FRAGMENT ||
|
||||
nexthdr == IPPROTO_HOPOPTS ||
|
||||
nexthdr == IPPROTO_SCTP))
|
||||
return -1;
|
||||
hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
|
||||
hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(nexthdr));
|
||||
|
||||
csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
|
||||
sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
|
||||
csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
|
||||
csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
|
||||
csum_pseudo_hdr = csum_add(csum_pseudo_hdr,
|
||||
(__force __wsum)htons(nexthdr));
|
||||
|
||||
skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
|
||||
skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
|
||||
|
|
@ -625,11 +633,10 @@ static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
|
|||
}
|
||||
|
||||
if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
|
||||
get_fixed_ipv4_csum(hw_checksum, skb, hdr);
|
||||
return get_fixed_ipv4_csum(hw_checksum, skb, hdr);
|
||||
#if IS_ENABLED(CONFIG_IPV6)
|
||||
else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
|
||||
if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
|
||||
return -1;
|
||||
if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
|
||||
return get_fixed_ipv6_csum(hw_checksum, skb, hdr);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ struct ppp {
|
|||
int n_channels; /* how many channels are attached 54 */
|
||||
spinlock_t rlock; /* lock for receive side 58 */
|
||||
spinlock_t wlock; /* lock for transmit side 5c */
|
||||
int *xmit_recursion __percpu; /* xmit recursion detect */
|
||||
int mru; /* max receive unit 60 */
|
||||
unsigned int flags; /* control bits 64 */
|
||||
unsigned int xstate; /* transmit state bits 68 */
|
||||
|
|
@ -1025,6 +1026,7 @@ static int ppp_dev_configure(struct net *src_net, struct net_device *dev,
|
|||
struct ppp *ppp = netdev_priv(dev);
|
||||
int indx;
|
||||
int err;
|
||||
int cpu;
|
||||
|
||||
ppp->dev = dev;
|
||||
ppp->ppp_net = src_net;
|
||||
|
|
@ -1039,6 +1041,15 @@ static int ppp_dev_configure(struct net *src_net, struct net_device *dev,
|
|||
INIT_LIST_HEAD(&ppp->channels);
|
||||
spin_lock_init(&ppp->rlock);
|
||||
spin_lock_init(&ppp->wlock);
|
||||
|
||||
ppp->xmit_recursion = alloc_percpu(int);
|
||||
if (!ppp->xmit_recursion) {
|
||||
err = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
for_each_possible_cpu(cpu)
|
||||
(*per_cpu_ptr(ppp->xmit_recursion, cpu)) = 0;
|
||||
|
||||
#ifdef CONFIG_PPP_MULTILINK
|
||||
ppp->minseq = -1;
|
||||
skb_queue_head_init(&ppp->mrq);
|
||||
|
|
@ -1050,11 +1061,15 @@ static int ppp_dev_configure(struct net *src_net, struct net_device *dev,
|
|||
|
||||
err = ppp_unit_register(ppp, conf->unit, conf->ifname_is_set);
|
||||
if (err < 0)
|
||||
return err;
|
||||
goto err2;
|
||||
|
||||
conf->file->private_data = &ppp->file;
|
||||
|
||||
return 0;
|
||||
err2:
|
||||
free_percpu(ppp->xmit_recursion);
|
||||
err1:
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct nla_policy ppp_nl_policy[IFLA_PPP_MAX + 1] = {
|
||||
|
|
@ -1398,18 +1413,16 @@ static void __ppp_xmit_process(struct ppp *ppp)
|
|||
ppp_xmit_unlock(ppp);
|
||||
}
|
||||
|
||||
static DEFINE_PER_CPU(int, ppp_xmit_recursion);
|
||||
|
||||
static void ppp_xmit_process(struct ppp *ppp)
|
||||
{
|
||||
local_bh_disable();
|
||||
|
||||
if (unlikely(__this_cpu_read(ppp_xmit_recursion)))
|
||||
if (unlikely(*this_cpu_ptr(ppp->xmit_recursion)))
|
||||
goto err;
|
||||
|
||||
__this_cpu_inc(ppp_xmit_recursion);
|
||||
(*this_cpu_ptr(ppp->xmit_recursion))++;
|
||||
__ppp_xmit_process(ppp);
|
||||
__this_cpu_dec(ppp_xmit_recursion);
|
||||
(*this_cpu_ptr(ppp->xmit_recursion))--;
|
||||
|
||||
local_bh_enable();
|
||||
|
||||
|
|
@ -1900,23 +1913,23 @@ static void __ppp_channel_push(struct channel *pch)
|
|||
spin_unlock_bh(&pch->downl);
|
||||
/* see if there is anything from the attached unit to be sent */
|
||||
if (skb_queue_empty(&pch->file.xq)) {
|
||||
read_lock_bh(&pch->upl);
|
||||
ppp = pch->ppp;
|
||||
if (ppp)
|
||||
__ppp_xmit_process(ppp);
|
||||
read_unlock_bh(&pch->upl);
|
||||
}
|
||||
}
|
||||
|
||||
static void ppp_channel_push(struct channel *pch)
|
||||
{
|
||||
local_bh_disable();
|
||||
|
||||
__this_cpu_inc(ppp_xmit_recursion);
|
||||
__ppp_channel_push(pch);
|
||||
__this_cpu_dec(ppp_xmit_recursion);
|
||||
|
||||
local_bh_enable();
|
||||
read_lock_bh(&pch->upl);
|
||||
if (pch->ppp) {
|
||||
(*this_cpu_ptr(pch->ppp->xmit_recursion))++;
|
||||
__ppp_channel_push(pch);
|
||||
(*this_cpu_ptr(pch->ppp->xmit_recursion))--;
|
||||
} else {
|
||||
__ppp_channel_push(pch);
|
||||
}
|
||||
read_unlock_bh(&pch->upl);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -3055,6 +3068,7 @@ static void ppp_destroy_interface(struct ppp *ppp)
|
|||
#endif /* CONFIG_PPP_FILTER */
|
||||
|
||||
kfree_skb(ppp->xmit_pending);
|
||||
free_percpu(ppp->xmit_recursion);
|
||||
|
||||
free_netdev(ppp->dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1340,10 +1340,14 @@ static int qmi_wwan_probe(struct usb_interface *intf,
|
|||
static void qmi_wwan_disconnect(struct usb_interface *intf)
|
||||
{
|
||||
struct usbnet *dev = usb_get_intfdata(intf);
|
||||
struct qmi_wwan_state *info = (void *)&dev->data;
|
||||
struct qmi_wwan_state *info;
|
||||
struct list_head *iter;
|
||||
struct net_device *ldev;
|
||||
|
||||
/* called twice if separate control and data intf */
|
||||
if (!dev)
|
||||
return;
|
||||
info = (void *)&dev->data;
|
||||
if (info->flags & QMI_WWAN_FLAG_MUX) {
|
||||
if (!rtnl_trylock()) {
|
||||
restart_syscall();
|
||||
|
|
|
|||
|
|
@ -4069,40 +4069,6 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
|
|||
return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
|
||||
}
|
||||
|
||||
static int __pci_dev_reset(struct pci_dev *dev, int probe)
|
||||
{
|
||||
int rc;
|
||||
|
||||
might_sleep();
|
||||
|
||||
rc = pci_dev_specific_reset(dev, probe);
|
||||
if (rc != -ENOTTY)
|
||||
goto done;
|
||||
|
||||
if (pcie_has_flr(dev)) {
|
||||
if (!probe)
|
||||
pcie_flr(dev);
|
||||
rc = 0;
|
||||
goto done;
|
||||
}
|
||||
|
||||
rc = pci_af_flr(dev, probe);
|
||||
if (rc != -ENOTTY)
|
||||
goto done;
|
||||
|
||||
rc = pci_pm_reset(dev, probe);
|
||||
if (rc != -ENOTTY)
|
||||
goto done;
|
||||
|
||||
rc = pci_dev_reset_slot_function(dev, probe);
|
||||
if (rc != -ENOTTY)
|
||||
goto done;
|
||||
|
||||
rc = pci_parent_bus_reset(dev, probe);
|
||||
done:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void pci_dev_lock(struct pci_dev *dev)
|
||||
{
|
||||
pci_cfg_access_lock(dev);
|
||||
|
|
@ -4141,6 +4107,12 @@ static void pci_reset_notify(struct pci_dev *dev, bool prepare)
|
|||
{
|
||||
const struct pci_error_handlers *err_handler =
|
||||
dev->driver ? dev->driver->err_handler : NULL;
|
||||
|
||||
/*
|
||||
* dev->driver->err_handler->reset_notify() is protected against
|
||||
* races with ->remove() by the device lock, which must be held by
|
||||
* the caller.
|
||||
*/
|
||||
if (err_handler && err_handler->reset_notify)
|
||||
err_handler->reset_notify(dev, prepare);
|
||||
}
|
||||
|
|
@ -4173,21 +4145,6 @@ static void pci_dev_restore(struct pci_dev *dev)
|
|||
pci_reset_notify(dev, false);
|
||||
}
|
||||
|
||||
static int pci_dev_reset(struct pci_dev *dev, int probe)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!probe)
|
||||
pci_dev_lock(dev);
|
||||
|
||||
rc = __pci_dev_reset(dev, probe);
|
||||
|
||||
if (!probe)
|
||||
pci_dev_unlock(dev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* __pci_reset_function - reset a PCI device function
|
||||
* @dev: PCI device to reset
|
||||
|
|
@ -4207,7 +4164,13 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
|
|||
*/
|
||||
int __pci_reset_function(struct pci_dev *dev)
|
||||
{
|
||||
return pci_dev_reset(dev, 0);
|
||||
int ret;
|
||||
|
||||
pci_dev_lock(dev);
|
||||
ret = __pci_reset_function_locked(dev);
|
||||
pci_dev_unlock(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__pci_reset_function);
|
||||
|
||||
|
|
@ -4232,7 +4195,27 @@ EXPORT_SYMBOL_GPL(__pci_reset_function);
|
|||
*/
|
||||
int __pci_reset_function_locked(struct pci_dev *dev)
|
||||
{
|
||||
return __pci_dev_reset(dev, 0);
|
||||
int rc;
|
||||
|
||||
might_sleep();
|
||||
|
||||
rc = pci_dev_specific_reset(dev, 0);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
if (pcie_has_flr(dev)) {
|
||||
pcie_flr(dev);
|
||||
return 0;
|
||||
}
|
||||
rc = pci_af_flr(dev, 0);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
rc = pci_pm_reset(dev, 0);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
rc = pci_dev_reset_slot_function(dev, 0);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
return pci_parent_bus_reset(dev, 0);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
|
||||
|
||||
|
|
@ -4249,7 +4232,26 @@ EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
|
|||
*/
|
||||
int pci_probe_reset_function(struct pci_dev *dev)
|
||||
{
|
||||
return pci_dev_reset(dev, 1);
|
||||
int rc;
|
||||
|
||||
might_sleep();
|
||||
|
||||
rc = pci_dev_specific_reset(dev, 1);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
if (pcie_has_flr(dev))
|
||||
return 0;
|
||||
rc = pci_af_flr(dev, 1);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
rc = pci_pm_reset(dev, 1);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
rc = pci_dev_reset_slot_function(dev, 1);
|
||||
if (rc != -ENOTTY)
|
||||
return rc;
|
||||
|
||||
return pci_parent_bus_reset(dev, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -4272,19 +4274,56 @@ int pci_reset_function(struct pci_dev *dev)
|
|||
{
|
||||
int rc;
|
||||
|
||||
rc = pci_dev_reset(dev, 1);
|
||||
rc = pci_probe_reset_function(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
pci_dev_lock(dev);
|
||||
pci_dev_save_and_disable(dev);
|
||||
|
||||
rc = __pci_reset_function_locked(dev);
|
||||
|
||||
pci_dev_restore(dev);
|
||||
pci_dev_unlock(dev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_reset_function);
|
||||
|
||||
/**
|
||||
* pci_reset_function_locked - quiesce and reset a PCI device function
|
||||
* @dev: PCI device to reset
|
||||
*
|
||||
* Some devices allow an individual function to be reset without affecting
|
||||
* other functions in the same device. The PCI device must be responsive
|
||||
* to PCI config space in order to use this function.
|
||||
*
|
||||
* This function does not just reset the PCI portion of a device, but
|
||||
* clears all the state associated with the device. This function differs
|
||||
* from __pci_reset_function() in that it saves and restores device state
|
||||
* over the reset. It also differs from pci_reset_function() in that it
|
||||
* requires the PCI device lock to be held.
|
||||
*
|
||||
* Returns 0 if the device function was successfully reset or negative if the
|
||||
* device doesn't support resetting a single function.
|
||||
*/
|
||||
int pci_reset_function_locked(struct pci_dev *dev)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = pci_probe_reset_function(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
pci_dev_save_and_disable(dev);
|
||||
|
||||
rc = pci_dev_reset(dev, 0);
|
||||
rc = __pci_reset_function_locked(dev);
|
||||
|
||||
pci_dev_restore(dev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_reset_function);
|
||||
EXPORT_SYMBOL_GPL(pci_reset_function_locked);
|
||||
|
||||
/**
|
||||
* pci_try_reset_function - quiesce and reset a PCI device function
|
||||
|
|
@ -4296,20 +4335,18 @@ int pci_try_reset_function(struct pci_dev *dev)
|
|||
{
|
||||
int rc;
|
||||
|
||||
rc = pci_dev_reset(dev, 1);
|
||||
rc = pci_probe_reset_function(dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
pci_dev_save_and_disable(dev);
|
||||
if (!pci_dev_trylock(dev))
|
||||
return -EAGAIN;
|
||||
|
||||
if (pci_dev_trylock(dev)) {
|
||||
rc = __pci_dev_reset(dev, 0);
|
||||
pci_dev_unlock(dev);
|
||||
} else
|
||||
rc = -EAGAIN;
|
||||
pci_dev_save_and_disable(dev);
|
||||
rc = __pci_reset_function_locked(dev);
|
||||
pci_dev_unlock(dev);
|
||||
|
||||
pci_dev_restore(dev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_try_reset_function);
|
||||
|
|
@ -4459,7 +4496,9 @@ static void pci_bus_save_and_disable(struct pci_bus *bus)
|
|||
struct pci_dev *dev;
|
||||
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
pci_dev_lock(dev);
|
||||
pci_dev_save_and_disable(dev);
|
||||
pci_dev_unlock(dev);
|
||||
if (dev->subordinate)
|
||||
pci_bus_save_and_disable(dev->subordinate);
|
||||
}
|
||||
|
|
@ -4474,7 +4513,9 @@ static void pci_bus_restore(struct pci_bus *bus)
|
|||
struct pci_dev *dev;
|
||||
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
pci_dev_lock(dev);
|
||||
pci_dev_restore(dev);
|
||||
pci_dev_unlock(dev);
|
||||
if (dev->subordinate)
|
||||
pci_bus_restore(dev->subordinate);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1547,6 +1547,13 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
|
|||
DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "HP Chromebook 11 G5 (Setzer)",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.ident = "Acer Chromebook R11 (Cyan)",
|
||||
.matches = {
|
||||
|
|
|
|||
|
|
@ -343,9 +343,9 @@ static const struct pinctrl_pin_desc mrfld_pins[] = {
|
|||
|
||||
static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
|
||||
static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
|
||||
static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 };
|
||||
static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 };
|
||||
static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 };
|
||||
static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
|
||||
static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
|
||||
static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
|
||||
static const unsigned int mrfld_pwm0_pins[] = { 144 };
|
||||
static const unsigned int mrfld_pwm1_pins[] = { 145 };
|
||||
static const unsigned int mrfld_pwm2_pins[] = { 132 };
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
|
|||
MESON_PIN(GPIODV_15, EE_OFF),
|
||||
MESON_PIN(GPIODV_16, EE_OFF),
|
||||
MESON_PIN(GPIODV_17, EE_OFF),
|
||||
MESON_PIN(GPIODV_18, EE_OFF),
|
||||
MESON_PIN(GPIODV_19, EE_OFF),
|
||||
MESON_PIN(GPIODV_20, EE_OFF),
|
||||
MESON_PIN(GPIODV_21, EE_OFF),
|
||||
|
|
|
|||
|
|
@ -89,6 +89,7 @@ static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {
|
|||
MESON_PIN(GPIODV_15, EE_OFF),
|
||||
MESON_PIN(GPIODV_16, EE_OFF),
|
||||
MESON_PIN(GPIODV_17, EE_OFF),
|
||||
MESON_PIN(GPIODV_18, EE_OFF),
|
||||
MESON_PIN(GPIODV_19, EE_OFF),
|
||||
MESON_PIN(GPIODV_20, EE_OFF),
|
||||
MESON_PIN(GPIODV_21, EE_OFF),
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ const struct armada_37xx_pin_data armada_37xx_pin_nb = {
|
|||
};
|
||||
|
||||
const struct armada_37xx_pin_data armada_37xx_pin_sb = {
|
||||
.nr_pins = 29,
|
||||
.nr_pins = 30,
|
||||
.name = "GPIO2",
|
||||
.groups = armada_37xx_sb_groups,
|
||||
.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
|
||||
|
|
|
|||
|
|
@ -205,8 +205,6 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
|
|||
|
||||
spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
exynos_irq_unmask(irqd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -226,8 +224,6 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
|
|||
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
|
||||
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
|
||||
|
||||
exynos_irq_mask(irqd);
|
||||
|
||||
spin_lock_irqsave(&bank->slock, flags);
|
||||
|
||||
con = readl(bank->eint_base + reg_con);
|
||||
|
|
|
|||
|
|
@ -811,6 +811,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
|
|||
SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
|
||||
SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
|
||||
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
|
||||
SUNXI_FUNCTION(0x5, "sim"), /* DET */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
|
||||
SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
|
||||
|
|
|
|||
|
|
@ -508,57 +508,71 @@ static const unsigned usb1_pins[] = {48, 49};
|
|||
static const int usb1_muxvals[] = {0, 0};
|
||||
static const unsigned usb2_pins[] = {50, 51};
|
||||
static const int usb2_muxvals[] = {0, 0};
|
||||
static const unsigned port_range_pins[] = {
|
||||
static const unsigned port_range0_pins[] = {
|
||||
159, 160, 161, 162, 163, 164, 165, 166, /* PORT0x */
|
||||
0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */
|
||||
8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */
|
||||
16, 17, 18, -1, -1, -1, -1, -1, /* PORT3x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */
|
||||
-1, -1, -1, 46, 47, 48, 49, 50, /* PORT5x */
|
||||
51, -1, -1, 54, 55, 56, 57, 58, /* PORT6x */
|
||||
16, 17, 18, /* PORT30-32 */
|
||||
};
|
||||
static const int port_range0_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
|
||||
15, 15, 15, /* PORT30-32 */
|
||||
};
|
||||
static const unsigned port_range1_pins[] = {
|
||||
46, 47, 48, 49, 50, /* PORT53-57 */
|
||||
51, /* PORT60 */
|
||||
};
|
||||
static const int port_range1_muxvals[] = {
|
||||
15, 15, 15, 15, 15, /* PORT53-57 */
|
||||
15, /* PORT60 */
|
||||
};
|
||||
static const unsigned port_range2_pins[] = {
|
||||
54, 55, 56, 57, 58, /* PORT63-67 */
|
||||
59, 60, 69, 70, 71, 72, 73, 74, /* PORT7x */
|
||||
75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */
|
||||
83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */
|
||||
91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
|
||||
99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
|
||||
107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
|
||||
115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
|
||||
61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
|
||||
123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
|
||||
131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
|
||||
139, 140, 141, 142, -1, -1, -1, -1, /* PORT22x */
|
||||
147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
|
||||
155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */
|
||||
};
|
||||
static const int port_range_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
|
||||
15, 15, 15, -1, -1, -1, -1, -1, /* PORT3x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */
|
||||
-1, -1, -1, 15, 15, 15, 15, 15, /* PORT5x */
|
||||
15, -1, -1, 15, 15, 15, 15, 15, /* PORT6x */
|
||||
static const int port_range2_muxvals[] = {
|
||||
15, 15, 15, 15, 15, /* PORT63-67 */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
|
||||
};
|
||||
static const unsigned port_range3_pins[] = {
|
||||
99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
|
||||
107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
|
||||
115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
|
||||
};
|
||||
static const int port_range3_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
|
||||
};
|
||||
static const unsigned port_range4_pins[] = {
|
||||
61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
|
||||
};
|
||||
static const int port_range4_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
|
||||
};
|
||||
static const unsigned port_range5_pins[] = {
|
||||
123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
|
||||
131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
|
||||
139, 140, 141, 142, /* PORT220-223 */
|
||||
};
|
||||
static const int port_range5_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
|
||||
15, 15, 15, 15, -1, -1, -1, -1, /* PORT22x */
|
||||
15, 15, 15, 15, /* PORT220-223 */
|
||||
};
|
||||
static const unsigned port_range6_pins[] = {
|
||||
147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
|
||||
155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */
|
||||
};
|
||||
static const int port_range6_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
|
||||
};
|
||||
|
|
@ -607,147 +621,153 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
|
|||
UNIPHIER_PINCTRL_GROUP(usb0),
|
||||
UNIPHIER_PINCTRL_GROUP(usb1),
|
||||
UNIPHIER_PINCTRL_GROUP(usb2),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range4),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range5),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range6),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range1, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range1, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range1, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range1, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range1, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range1, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range2, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range2, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range2, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range2, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range2, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range2, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range2, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range2, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range2, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range2, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range2, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range2, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range2, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range2, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range2, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range2, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range2, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range2, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range2, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range2, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range2, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range2, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range2, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range2, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range2, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range2, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range2, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range2, 27),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range2, 28),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range2, 29),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range2, 30),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range2, 31),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range2, 32),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range2, 33),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range2, 34),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range2, 35),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range2, 36),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range3, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range3, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range3, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range3, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range3, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range3, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range3, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range3, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range3, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range3, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range3, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range3, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range3, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range3, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range3, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range3, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range3, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range3, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range3, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range3, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range3, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range3, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range3, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range3, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range4, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range4, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range4, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range4, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range4, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range4, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range4, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range4, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range5, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range5, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range5, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range5, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range5, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range5, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range5, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range5, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range5, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range5, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range5, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range5, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range5, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range5, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range5, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range5, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range5, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range5, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range5, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range5, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range6, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range6, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range6, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range6, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range6, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range6, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range6, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range6, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range6, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range6, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range6, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range6, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range6, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range6, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range6, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range6, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
|
||||
|
|
|
|||
|
|
@ -597,7 +597,7 @@ static const unsigned usb2_pins[] = {50, 51};
|
|||
static const int usb2_muxvals[] = {0, 0};
|
||||
static const unsigned usb3_pins[] = {52, 53};
|
||||
static const int usb3_muxvals[] = {0, 0};
|
||||
static const unsigned port_range_pins[] = {
|
||||
static const unsigned port_range0_pins[] = {
|
||||
168, 169, 170, 171, 172, 173, 174, 175, /* PORT0x */
|
||||
0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */
|
||||
8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */
|
||||
|
|
@ -609,23 +609,8 @@ static const unsigned port_range_pins[] = {
|
|||
75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */
|
||||
83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */
|
||||
91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
|
||||
99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
|
||||
107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
|
||||
115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
|
||||
61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
|
||||
123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
|
||||
131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
|
||||
139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */
|
||||
147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
|
||||
155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */
|
||||
163, 164, 165, 166, 167, /* PORT25x */
|
||||
};
|
||||
static const int port_range_muxvals[] = {
|
||||
static const int port_range0_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
|
||||
|
|
@ -637,21 +622,38 @@ static const int port_range_muxvals[] = {
|
|||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
|
||||
};
|
||||
static const unsigned port_range1_pins[] = {
|
||||
99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
|
||||
107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
|
||||
115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
|
||||
};
|
||||
static const int port_range1_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
|
||||
};
|
||||
static const unsigned port_range2_pins[] = {
|
||||
61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
|
||||
};
|
||||
static const int port_range2_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
|
||||
};
|
||||
static const unsigned port_range3_pins[] = {
|
||||
123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
|
||||
131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
|
||||
139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */
|
||||
147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
|
||||
155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */
|
||||
163, 164, 165, 166, 167, /* PORT250-254 */
|
||||
};
|
||||
static const int port_range3_muxvals[] = {
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
|
||||
15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
|
||||
15, 15, 15, 15, 15, /* PORT25x */
|
||||
15, 15, 15, 15, 15, /* PORT250-254 */
|
||||
};
|
||||
static const unsigned xirq_pins[] = {
|
||||
149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */
|
||||
|
|
@ -695,174 +697,177 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
|
|||
UNIPHIER_PINCTRL_GROUP(usb1),
|
||||
UNIPHIER_PINCTRL_GROUP(usb2),
|
||||
UNIPHIER_PINCTRL_GROUP(usb3),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
|
||||
UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range, 27),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range, 28),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range, 29),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range, 30),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range, 31),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range, 32),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range, 33),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range, 34),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range, 35),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range, 36),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range, 37),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range, 38),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range, 39),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range, 40),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range, 41),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range, 42),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range, 49),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range, 50),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range, 180),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range, 181),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range, 182),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range, 183),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range, 200),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range, 201),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range, 202),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range, 203),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range, 204),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range2, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range2, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range2, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range2, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range2, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range2, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range2, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range2, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range3, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range3, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range3, 2),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range3, 3),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range3, 4),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range3, 5),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range3, 6),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range3, 7),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range3, 8),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range3, 9),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range3, 10),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range3, 11),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range3, 12),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range3, 13),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range3, 14),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range3, 15),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range3, 16),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range3, 17),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range3, 18),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range3, 19),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range3, 20),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range3, 21),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range3, 22),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range3, 23),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range3, 24),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range3, 25),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range3, 26),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range3, 27),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range3, 28),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range3, 29),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range3, 30),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range3, 31),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range3, 32),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range3, 33),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range3, 34),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range3, 35),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range3, 36),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range3, 37),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range3, 38),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range3, 39),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range3, 40),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range3, 41),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range3, 42),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range3, 43),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range3, 44),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
|
||||
UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
|
||||
|
|
|
|||
|
|
@ -751,29 +751,6 @@ sg_new_write(Sg_fd *sfp, struct file *file, const char __user *buf,
|
|||
return count;
|
||||
}
|
||||
|
||||
static bool sg_is_valid_dxfer(sg_io_hdr_t *hp)
|
||||
{
|
||||
switch (hp->dxfer_direction) {
|
||||
case SG_DXFER_NONE:
|
||||
if (hp->dxferp || hp->dxfer_len > 0)
|
||||
return false;
|
||||
return true;
|
||||
case SG_DXFER_TO_DEV:
|
||||
case SG_DXFER_FROM_DEV:
|
||||
case SG_DXFER_TO_FROM_DEV:
|
||||
if (!hp->dxferp || hp->dxfer_len == 0)
|
||||
return false;
|
||||
return true;
|
||||
case SG_DXFER_UNKNOWN:
|
||||
if ((!hp->dxferp && hp->dxfer_len) ||
|
||||
(hp->dxferp && hp->dxfer_len == 0))
|
||||
return false;
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
sg_common_write(Sg_fd * sfp, Sg_request * srp,
|
||||
unsigned char *cmnd, int timeout, int blocking)
|
||||
|
|
@ -794,7 +771,7 @@ sg_common_write(Sg_fd * sfp, Sg_request * srp,
|
|||
"sg_common_write: scsi opcode=0x%02x, cmd_size=%d\n",
|
||||
(int) cmnd[0], (int) hp->cmd_len));
|
||||
|
||||
if (!sg_is_valid_dxfer(hp))
|
||||
if (hp->dxfer_len >= SZ_256M)
|
||||
return -EINVAL;
|
||||
|
||||
k = sg_start_req(srp, cmnd);
|
||||
|
|
|
|||
|
|
@ -2396,6 +2396,7 @@ static ssize_t comedi_write(struct file *file, const char __user *buf,
|
|||
continue;
|
||||
}
|
||||
|
||||
set_current_state(TASK_RUNNING);
|
||||
wp = async->buf_write_ptr;
|
||||
n1 = min(n, async->prealloc_bufsz - wp);
|
||||
n2 = n - n1;
|
||||
|
|
@ -2528,6 +2529,8 @@ static ssize_t comedi_read(struct file *file, char __user *buf, size_t nbytes,
|
|||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
set_current_state(TASK_RUNNING);
|
||||
rp = async->buf_read_ptr;
|
||||
n1 = min(n, async->prealloc_bufsz - rp);
|
||||
n2 = n - n1;
|
||||
|
|
|
|||
|
|
@ -472,7 +472,7 @@ static int ad2s1210_read_raw(struct iio_dev *indio_dev,
|
|||
long m)
|
||||
{
|
||||
struct ad2s1210_state *st = iio_priv(indio_dev);
|
||||
bool negative;
|
||||
u16 negative;
|
||||
int ret = 0;
|
||||
u16 pos;
|
||||
s16 vel;
|
||||
|
|
|
|||
|
|
@ -418,6 +418,7 @@ int iscsit_reset_np_thread(
|
|||
return 0;
|
||||
}
|
||||
np->np_thread_state = ISCSI_NP_THREAD_RESET;
|
||||
atomic_inc(&np->np_reset_count);
|
||||
|
||||
if (np->np_thread) {
|
||||
spin_unlock_bh(&np->np_thread_lock);
|
||||
|
|
@ -2173,6 +2174,7 @@ iscsit_setup_text_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
|
|||
cmd->cmd_sn = be32_to_cpu(hdr->cmdsn);
|
||||
cmd->exp_stat_sn = be32_to_cpu(hdr->exp_statsn);
|
||||
cmd->data_direction = DMA_NONE;
|
||||
kfree(cmd->text_in_ptr);
|
||||
cmd->text_in_ptr = NULL;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1237,9 +1237,11 @@ static int __iscsi_target_login_thread(struct iscsi_np *np)
|
|||
flush_signals(current);
|
||||
|
||||
spin_lock_bh(&np->np_thread_lock);
|
||||
if (np->np_thread_state == ISCSI_NP_THREAD_RESET) {
|
||||
if (atomic_dec_if_positive(&np->np_reset_count) >= 0) {
|
||||
np->np_thread_state = ISCSI_NP_THREAD_ACTIVE;
|
||||
spin_unlock_bh(&np->np_thread_lock);
|
||||
complete(&np->np_restart_comp);
|
||||
return 1;
|
||||
} else if (np->np_thread_state == ISCSI_NP_THREAD_SHUTDOWN) {
|
||||
spin_unlock_bh(&np->np_thread_lock);
|
||||
goto exit;
|
||||
|
|
@ -1272,7 +1274,8 @@ static int __iscsi_target_login_thread(struct iscsi_np *np)
|
|||
goto exit;
|
||||
} else if (rc < 0) {
|
||||
spin_lock_bh(&np->np_thread_lock);
|
||||
if (np->np_thread_state == ISCSI_NP_THREAD_RESET) {
|
||||
if (atomic_dec_if_positive(&np->np_reset_count) >= 0) {
|
||||
np->np_thread_state = ISCSI_NP_THREAD_ACTIVE;
|
||||
spin_unlock_bh(&np->np_thread_lock);
|
||||
complete(&np->np_restart_comp);
|
||||
iscsit_put_transport(conn->conn_transport);
|
||||
|
|
|
|||
|
|
@ -364,7 +364,7 @@ void core_tpg_del_initiator_node_acl(struct se_node_acl *acl)
|
|||
mutex_lock(&tpg->acl_node_mutex);
|
||||
if (acl->dynamic_node_acl)
|
||||
acl->dynamic_node_acl = 0;
|
||||
list_del(&acl->acl_list);
|
||||
list_del_init(&acl->acl_list);
|
||||
mutex_unlock(&tpg->acl_node_mutex);
|
||||
|
||||
target_shutdown_sessions(acl);
|
||||
|
|
@ -548,7 +548,7 @@ int core_tpg_deregister(struct se_portal_group *se_tpg)
|
|||
* in transport_deregister_session().
|
||||
*/
|
||||
list_for_each_entry_safe(nacl, nacl_tmp, &node_list, acl_list) {
|
||||
list_del(&nacl->acl_list);
|
||||
list_del_init(&nacl->acl_list);
|
||||
|
||||
core_tpg_wait_for_nacl_pr_ref(nacl);
|
||||
core_free_device_list_for_node(nacl, se_tpg);
|
||||
|
|
|
|||
|
|
@ -466,7 +466,7 @@ static void target_complete_nacl(struct kref *kref)
|
|||
}
|
||||
|
||||
mutex_lock(&se_tpg->acl_node_mutex);
|
||||
list_del(&nacl->acl_list);
|
||||
list_del_init(&nacl->acl_list);
|
||||
mutex_unlock(&se_tpg->acl_node_mutex);
|
||||
|
||||
core_tpg_wait_for_nacl_pr_ref(nacl);
|
||||
|
|
@ -538,7 +538,7 @@ void transport_free_session(struct se_session *se_sess)
|
|||
spin_unlock_irqrestore(&se_nacl->nacl_sess_lock, flags);
|
||||
|
||||
if (se_nacl->dynamic_stop)
|
||||
list_del(&se_nacl->acl_list);
|
||||
list_del_init(&se_nacl->acl_list);
|
||||
}
|
||||
mutex_unlock(&se_tpg->acl_node_mutex);
|
||||
|
||||
|
|
|
|||
|
|
@ -1878,7 +1878,7 @@ void usb_hcd_flush_endpoint(struct usb_device *udev,
|
|||
/* No more submits can occur */
|
||||
spin_lock_irq(&hcd_urb_list_lock);
|
||||
rescan:
|
||||
list_for_each_entry (urb, &ep->urb_list, urb_list) {
|
||||
list_for_each_entry_reverse(urb, &ep->urb_list, urb_list) {
|
||||
int is_in;
|
||||
|
||||
if (urb->unlinked)
|
||||
|
|
@ -2475,6 +2475,8 @@ void usb_hc_died (struct usb_hcd *hcd)
|
|||
}
|
||||
if (usb_hcd_is_primary_hcd(hcd) && hcd->shared_hcd) {
|
||||
hcd = hcd->shared_hcd;
|
||||
clear_bit(HCD_FLAG_RH_RUNNING, &hcd->flags);
|
||||
set_bit(HCD_FLAG_DEAD, &hcd->flags);
|
||||
if (hcd->rh_registered) {
|
||||
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -4730,7 +4730,8 @@ hub_power_remaining(struct usb_hub *hub)
|
|||
static void hub_port_connect(struct usb_hub *hub, int port1, u16 portstatus,
|
||||
u16 portchange)
|
||||
{
|
||||
int status, i;
|
||||
int status = -ENODEV;
|
||||
int i;
|
||||
unsigned unit_load;
|
||||
struct usb_device *hdev = hub->hdev;
|
||||
struct usb_hcd *hcd = bus_to_hcd(hdev->bus);
|
||||
|
|
@ -4934,9 +4935,10 @@ loop:
|
|||
|
||||
done:
|
||||
hub_port_disable(hub, port1, 1);
|
||||
if (hcd->driver->relinquish_port && !hub->hdev->parent)
|
||||
hcd->driver->relinquish_port(hcd, port1);
|
||||
|
||||
if (hcd->driver->relinquish_port && !hub->hdev->parent) {
|
||||
if (status != -ENOTCONN && status != -ENODEV)
|
||||
hcd->driver->relinquish_port(hcd, port1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle physical or logical connection change events.
|
||||
|
|
|
|||
|
|
@ -150,6 +150,9 @@ static const struct usb_device_id usb_quirk_list[] = {
|
|||
/* appletouch */
|
||||
{ USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
|
||||
/* Genesys Logic hub, internally used by Moshi USB to Ethernet Adapter */
|
||||
{ USB_DEVICE(0x05e3, 0x0616), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
/* Avision AV600U */
|
||||
{ USB_DEVICE(0x0638, 0x0a13), .driver_info =
|
||||
USB_QUIRK_STRING_FETCH_255 },
|
||||
|
|
@ -249,6 +252,7 @@ static const struct usb_device_id usb_amd_resume_quirk_list[] = {
|
|||
{ USB_DEVICE(0x093a, 0x2500), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
{ USB_DEVICE(0x093a, 0x2510), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
{ USB_DEVICE(0x093a, 0x2521), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
{ USB_DEVICE(0x03f0, 0x2b4a), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
|
||||
/* Logitech Optical Mouse M90/M100 */
|
||||
{ USB_DEVICE(0x046d, 0xc05a), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
|
|
|
|||
|
|
@ -758,21 +758,32 @@ static struct renesas_usb3_request *usb3_get_request(struct renesas_usb3_ep
|
|||
return usb3_req;
|
||||
}
|
||||
|
||||
static void __usb3_request_done(struct renesas_usb3_ep *usb3_ep,
|
||||
struct renesas_usb3_request *usb3_req,
|
||||
int status)
|
||||
{
|
||||
struct renesas_usb3 *usb3 = usb3_ep_to_usb3(usb3_ep);
|
||||
|
||||
dev_dbg(usb3_to_dev(usb3), "giveback: ep%2d, %u, %u, %d\n",
|
||||
usb3_ep->num, usb3_req->req.length, usb3_req->req.actual,
|
||||
status);
|
||||
usb3_req->req.status = status;
|
||||
usb3_ep->started = false;
|
||||
list_del_init(&usb3_req->queue);
|
||||
spin_unlock(&usb3->lock);
|
||||
usb_gadget_giveback_request(&usb3_ep->ep, &usb3_req->req);
|
||||
spin_lock(&usb3->lock);
|
||||
}
|
||||
|
||||
static void usb3_request_done(struct renesas_usb3_ep *usb3_ep,
|
||||
struct renesas_usb3_request *usb3_req, int status)
|
||||
{
|
||||
struct renesas_usb3 *usb3 = usb3_ep_to_usb3(usb3_ep);
|
||||
unsigned long flags;
|
||||
|
||||
dev_dbg(usb3_to_dev(usb3), "giveback: ep%2d, %u, %u, %d\n",
|
||||
usb3_ep->num, usb3_req->req.length, usb3_req->req.actual,
|
||||
status);
|
||||
usb3_req->req.status = status;
|
||||
spin_lock_irqsave(&usb3->lock, flags);
|
||||
usb3_ep->started = false;
|
||||
list_del_init(&usb3_req->queue);
|
||||
__usb3_request_done(usb3_ep, usb3_req, status);
|
||||
spin_unlock_irqrestore(&usb3->lock, flags);
|
||||
usb_gadget_giveback_request(&usb3_ep->ep, &usb3_req->req);
|
||||
}
|
||||
|
||||
static void usb3_irq_epc_pipe0_status_end(struct renesas_usb3 *usb3)
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ enum amd_chipset_gen {
|
|||
AMD_CHIPSET_HUDSON2,
|
||||
AMD_CHIPSET_BOLTON,
|
||||
AMD_CHIPSET_YANGTZE,
|
||||
AMD_CHIPSET_TAISHAN,
|
||||
AMD_CHIPSET_UNKNOWN,
|
||||
};
|
||||
|
||||
|
|
@ -141,6 +142,11 @@ static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
|
|||
pinfo->sb_type.gen = AMD_CHIPSET_SB700;
|
||||
else if (rev >= 0x40 && rev <= 0x4f)
|
||||
pinfo->sb_type.gen = AMD_CHIPSET_SB800;
|
||||
}
|
||||
pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
|
||||
0x145c, NULL);
|
||||
if (pinfo->smbus_dev) {
|
||||
pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
|
||||
} else {
|
||||
pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
|
||||
|
|
@ -260,11 +266,12 @@ int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
|
|||
{
|
||||
/* Make sure amd chipset type has already been initialized */
|
||||
usb_amd_find_chipset_info();
|
||||
if (amd_chipset.sb_type.gen != AMD_CHIPSET_YANGTZE)
|
||||
return 0;
|
||||
|
||||
dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
|
||||
return 1;
|
||||
if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
|
||||
amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
|
||||
dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
|
||||
|
||||
|
|
@ -1150,3 +1157,23 @@ static void quirk_usb_early_handoff(struct pci_dev *pdev)
|
|||
}
|
||||
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
|
||||
|
||||
bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)
|
||||
{
|
||||
/*
|
||||
* Our dear uPD72020{1,2} friend only partially resets when
|
||||
* asked to via the XHCI interface, and may end up doing DMA
|
||||
* at the wrong addresses, as it keeps the top 32bit of some
|
||||
* addresses from its previous programming under obscure
|
||||
* circumstances.
|
||||
* Give it a good wack at probe time. Unfortunately, this
|
||||
* needs to happen before we've had a chance to discover any
|
||||
* quirk, or the system will be in a rather bad state.
|
||||
*/
|
||||
if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
|
||||
(pdev->device == 0x0014 || pdev->device == 0x0015))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset);
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev);
|
|||
void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev);
|
||||
void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
|
||||
void sb800_prefetch(struct device *dev, int on);
|
||||
bool usb_xhci_needs_pci_reset(struct pci_dev *pdev);
|
||||
#else
|
||||
struct pci_dev;
|
||||
static inline void usb_amd_quirk_pll_disable(void) {}
|
||||
|
|
|
|||
|
|
@ -285,6 +285,13 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|||
|
||||
driver = (struct hc_driver *)id->driver_data;
|
||||
|
||||
/* For some HW implementation, a XHCI reset is just not enough... */
|
||||
if (usb_xhci_needs_pci_reset(dev)) {
|
||||
dev_info(&dev->dev, "Resetting\n");
|
||||
if (pci_reset_function_locked(dev))
|
||||
dev_warn(&dev->dev, "Reset failed");
|
||||
}
|
||||
|
||||
/* Prevent runtime suspending between USB-2 and USB-3 initialization */
|
||||
pm_runtime_get_noresume(&dev->dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
|
|||
"Could not flush host TX%d fifo: csr: %04x\n",
|
||||
ep->epnum, csr))
|
||||
return;
|
||||
mdelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,9 +20,13 @@
|
|||
/* Low Power Status register (LPSTS) */
|
||||
#define LPSTS_SUSPM 0x4000
|
||||
|
||||
/* USB General control register 2 (UGCTRL2), bit[31:6] should be 0 */
|
||||
/*
|
||||
* USB General control register 2 (UGCTRL2)
|
||||
* Remarks: bit[31:11] and bit[9:6] should be 0
|
||||
*/
|
||||
#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
|
||||
#define UGCTRL2_USB0SEL_OTG 0x00000030
|
||||
#define UGCTRL2_VBUSSEL 0x00000400
|
||||
|
||||
static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
|
||||
{
|
||||
|
|
@ -34,7 +38,8 @@ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
|
|||
{
|
||||
struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
|
||||
|
||||
usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG);
|
||||
usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG |
|
||||
UGCTRL2_VBUSSEL);
|
||||
|
||||
if (enable) {
|
||||
usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
|
||||
|
|
|
|||
|
|
@ -142,6 +142,7 @@ static const struct usb_device_id id_table[] = {
|
|||
{ USB_DEVICE(0x10C4, 0x8998) }, /* KCF Technologies PRN */
|
||||
{ USB_DEVICE(0x10C4, 0x8A2A) }, /* HubZ dual ZigBee and Z-Wave dongle */
|
||||
{ USB_DEVICE(0x10C4, 0x8A5E) }, /* CEL EM3588 ZigBee USB Stick Long Range */
|
||||
{ USB_DEVICE(0x10C4, 0x8B34) }, /* Qivicon ZigBee USB Radio Stick */
|
||||
{ USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */
|
||||
{ USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */
|
||||
{ USB_DEVICE(0x10C4, 0xEA70) }, /* Silicon Labs factory default */
|
||||
|
|
|
|||
|
|
@ -2025,6 +2025,8 @@ static const struct usb_device_id option_ids[] = {
|
|||
{ USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7d04, 0xff) }, /* D-Link DWM-158 */
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7e19, 0xff), /* D-Link DWM-221 B1 */
|
||||
.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
|
||||
{ USB_DEVICE_INTERFACE_CLASS(0x2001, 0x7e35, 0xff), /* D-Link DWM-222 */
|
||||
.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e01, 0xff, 0xff, 0xff) }, /* D-Link DWM-152/C1 */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e02, 0xff, 0xff, 0xff) }, /* D-Link DWM-156/C1 */
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x7e11, 0xff, 0xff, 0xff) }, /* D-Link DWM-156/A3 */
|
||||
|
|
|
|||
|
|
@ -52,6 +52,8 @@ static const struct usb_device_id id_table[] = {
|
|||
{ USB_DEVICE(IODATA_VENDOR_ID, IODATA_PRODUCT_ID_RSAQ5) },
|
||||
{ USB_DEVICE(ATEN_VENDOR_ID, ATEN_PRODUCT_ID),
|
||||
.driver_info = PL2303_QUIRK_ENDPOINT_HACK },
|
||||
{ USB_DEVICE(ATEN_VENDOR_ID, ATEN_PRODUCT_UC485),
|
||||
.driver_info = PL2303_QUIRK_ENDPOINT_HACK },
|
||||
{ USB_DEVICE(ATEN_VENDOR_ID, ATEN_PRODUCT_ID2) },
|
||||
{ USB_DEVICE(ATEN_VENDOR_ID2, ATEN_PRODUCT_ID) },
|
||||
{ USB_DEVICE(ELCOM_VENDOR_ID, ELCOM_PRODUCT_ID) },
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#define ATEN_VENDOR_ID 0x0557
|
||||
#define ATEN_VENDOR_ID2 0x0547
|
||||
#define ATEN_PRODUCT_ID 0x2008
|
||||
#define ATEN_PRODUCT_UC485 0x2021
|
||||
#define ATEN_PRODUCT_ID2 0x2118
|
||||
|
||||
#define IODATA_VENDOR_ID 0x04bb
|
||||
|
|
|
|||
|
|
@ -124,9 +124,9 @@ UNUSUAL_DEV(0x0bc2, 0xab2a, 0x0000, 0x9999,
|
|||
/* Reported-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> */
|
||||
UNUSUAL_DEV(0x13fd, 0x3940, 0x0000, 0x9999,
|
||||
"Initio Corporation",
|
||||
"",
|
||||
"INIC-3069",
|
||||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_NO_ATA_1X),
|
||||
US_FL_NO_ATA_1X | US_FL_IGNORE_RESIDUE),
|
||||
|
||||
/* Reported-by: Tom Arild Naess <tanaess@gmail.com> */
|
||||
UNUSUAL_DEV(0x152d, 0x0539, 0x0000, 0x9999,
|
||||
|
|
|
|||
|
|
@ -315,6 +315,7 @@ static int usb_stor_control_thread(void * __us)
|
|||
{
|
||||
struct us_data *us = (struct us_data *)__us;
|
||||
struct Scsi_Host *host = us_to_host(us);
|
||||
struct scsi_cmnd *srb;
|
||||
|
||||
for (;;) {
|
||||
usb_stor_dbg(us, "*** thread sleeping\n");
|
||||
|
|
@ -330,6 +331,7 @@ static int usb_stor_control_thread(void * __us)
|
|||
scsi_lock(host);
|
||||
|
||||
/* When we are called with no command pending, we're done */
|
||||
srb = us->srb;
|
||||
if (us->srb == NULL) {
|
||||
scsi_unlock(host);
|
||||
mutex_unlock(&us->dev_mutex);
|
||||
|
|
@ -398,14 +400,11 @@ static int usb_stor_control_thread(void * __us)
|
|||
/* lock access to the state */
|
||||
scsi_lock(host);
|
||||
|
||||
/* indicate that the command is done */
|
||||
if (us->srb->result != DID_ABORT << 16) {
|
||||
usb_stor_dbg(us, "scsi cmd done, result=0x%x\n",
|
||||
us->srb->result);
|
||||
us->srb->scsi_done(us->srb);
|
||||
} else {
|
||||
/* was the command aborted? */
|
||||
if (us->srb->result == DID_ABORT << 16) {
|
||||
SkipForAbort:
|
||||
usb_stor_dbg(us, "scsi command aborted\n");
|
||||
srb = NULL; /* Don't call srb->scsi_done() */
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -429,6 +428,13 @@ SkipForAbort:
|
|||
|
||||
/* unlock the device pointers */
|
||||
mutex_unlock(&us->dev_mutex);
|
||||
|
||||
/* now that the locks are released, notify the SCSI core */
|
||||
if (srb) {
|
||||
usb_stor_dbg(us, "scsi cmd done, result=0x%x\n",
|
||||
srb->result);
|
||||
srb->scsi_done(srb);
|
||||
}
|
||||
} /* for (;;) */
|
||||
|
||||
/* Wait until we are told to stop */
|
||||
|
|
|
|||
|
|
@ -4463,29 +4463,25 @@ try_submit_last:
|
|||
}
|
||||
|
||||
/*
|
||||
* Sanity check for fiemap cache
|
||||
* Emit last fiemap cache
|
||||
*
|
||||
* All fiemap cache should be submitted by emit_fiemap_extent()
|
||||
* Iteration should be terminated either by last fiemap extent or
|
||||
* fieinfo->fi_extents_max.
|
||||
* So no cached fiemap should exist.
|
||||
* The last fiemap cache may still be cached in the following case:
|
||||
* 0 4k 8k
|
||||
* |<- Fiemap range ->|
|
||||
* |<------------ First extent ----------->|
|
||||
*
|
||||
* In this case, the first extent range will be cached but not emitted.
|
||||
* So we must emit it before ending extent_fiemap().
|
||||
*/
|
||||
static int check_fiemap_cache(struct btrfs_fs_info *fs_info,
|
||||
struct fiemap_extent_info *fieinfo,
|
||||
struct fiemap_cache *cache)
|
||||
static int emit_last_fiemap_cache(struct btrfs_fs_info *fs_info,
|
||||
struct fiemap_extent_info *fieinfo,
|
||||
struct fiemap_cache *cache)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!cache->cached)
|
||||
return 0;
|
||||
|
||||
/* Small and recoverbale problem, only to info developer */
|
||||
#ifdef CONFIG_BTRFS_DEBUG
|
||||
WARN_ON(1);
|
||||
#endif
|
||||
btrfs_warn(fs_info,
|
||||
"unhandled fiemap cache detected: offset=%llu phys=%llu len=%llu flags=0x%x",
|
||||
cache->offset, cache->phys, cache->len, cache->flags);
|
||||
ret = fiemap_fill_next_extent(fieinfo, cache->offset, cache->phys,
|
||||
cache->len, cache->flags);
|
||||
cache->cached = false;
|
||||
|
|
@ -4701,7 +4697,7 @@ int extent_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
|
|||
}
|
||||
out_free:
|
||||
if (!ret)
|
||||
ret = check_fiemap_cache(root->fs_info, fieinfo, &cache);
|
||||
ret = emit_last_fiemap_cache(root->fs_info, fieinfo, &cache);
|
||||
free_extent_map(em);
|
||||
out:
|
||||
btrfs_free_path(path);
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ struct fuse_file *fuse_file_alloc(struct fuse_conn *fc)
|
|||
{
|
||||
struct fuse_file *ff;
|
||||
|
||||
ff = kmalloc(sizeof(struct fuse_file), GFP_KERNEL);
|
||||
ff = kzalloc(sizeof(struct fuse_file), GFP_KERNEL);
|
||||
if (unlikely(!ff))
|
||||
return NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ config PNFS_FILE_LAYOUT
|
|||
config PNFS_BLOCK
|
||||
tristate
|
||||
depends on NFS_V4_1 && BLK_DEV_DM
|
||||
depends on 64BIT || LBDAF
|
||||
default NFS_V4
|
||||
|
||||
config PNFS_FLEXFILE_LAYOUT
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ void nfs4_ff_layout_free_deviceid(struct nfs4_ff_layout_ds *mirror_ds)
|
|||
{
|
||||
nfs4_print_deviceid(&mirror_ds->id_node.deviceid);
|
||||
nfs4_pnfs_ds_put(mirror_ds->ds);
|
||||
kfree(mirror_ds->ds_versions);
|
||||
kfree_rcu(mirror_ds, id_node.rcu);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -519,6 +519,7 @@ xlog_discard_endio(
|
|||
|
||||
INIT_WORK(&ctx->discard_endio_work, xlog_discard_endio_work);
|
||||
queue_work(xfs_discard_wq, &ctx->discard_endio_work);
|
||||
bio_put(bio);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -105,6 +105,11 @@ struct st_sensor_fullscale {
|
|||
struct st_sensor_fullscale_avl fs_avl[ST_SENSORS_FULLSCALE_AVL_MAX];
|
||||
};
|
||||
|
||||
struct st_sensor_sim {
|
||||
u8 addr;
|
||||
u8 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct st_sensor_bdu - ST sensor device block data update
|
||||
* @addr: address of the register.
|
||||
|
|
@ -197,6 +202,7 @@ struct st_sensor_transfer_function {
|
|||
* @bdu: Block data update register.
|
||||
* @das: Data Alignment Selection register.
|
||||
* @drdy_irq: Data ready register of the sensor.
|
||||
* @sim: SPI serial interface mode register of the sensor.
|
||||
* @multi_read_bit: Use or not particular bit for [I2C/SPI] multi-read.
|
||||
* @bootime: samples to discard when sensor passing from power-down to power-up.
|
||||
*/
|
||||
|
|
@ -213,6 +219,7 @@ struct st_sensor_settings {
|
|||
struct st_sensor_bdu bdu;
|
||||
struct st_sensor_das das;
|
||||
struct st_sensor_data_ready_irq drdy_irq;
|
||||
struct st_sensor_sim sim;
|
||||
bool multi_read_bit;
|
||||
unsigned int bootime;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -638,10 +638,10 @@ struct nand_buffers {
|
|||
* @tWW_min: WP# transition to WE# low
|
||||
*/
|
||||
struct nand_sdr_timings {
|
||||
u32 tBERS_max;
|
||||
u64 tBERS_max;
|
||||
u32 tCCS_min;
|
||||
u32 tPROG_max;
|
||||
u32 tR_max;
|
||||
u64 tPROG_max;
|
||||
u64 tR_max;
|
||||
u32 tALH_min;
|
||||
u32 tADL_min;
|
||||
u32 tALS_min;
|
||||
|
|
|
|||
|
|
@ -1049,6 +1049,7 @@ void pcie_flr(struct pci_dev *dev);
|
|||
int __pci_reset_function(struct pci_dev *dev);
|
||||
int __pci_reset_function_locked(struct pci_dev *dev);
|
||||
int pci_reset_function(struct pci_dev *dev);
|
||||
int pci_reset_function_locked(struct pci_dev *dev);
|
||||
int pci_try_reset_function(struct pci_dev *dev);
|
||||
int pci_probe_reset_slot(struct pci_slot *slot);
|
||||
int pci_reset_slot(struct pci_slot *slot);
|
||||
|
|
|
|||
|
|
@ -17,10 +17,12 @@
|
|||
* Available only for accelerometer and pressure sensors.
|
||||
* Accelerometer DRDY on LSM330 available only on pin 1 (see datasheet).
|
||||
* @open_drain: set the interrupt line to be open drain if possible.
|
||||
* @spi_3wire: enable spi-3wire mode.
|
||||
*/
|
||||
struct st_sensors_platform_data {
|
||||
u8 drdy_int_pin;
|
||||
bool open_drain;
|
||||
bool spi_3wire;
|
||||
};
|
||||
|
||||
#endif /* ST_SENSORS_PDATA_H */
|
||||
|
|
|
|||
|
|
@ -787,6 +787,7 @@ struct iscsi_np {
|
|||
int np_sock_type;
|
||||
enum np_thread_state_table np_thread_state;
|
||||
bool enabled;
|
||||
atomic_t np_reset_count;
|
||||
enum iscsi_timer_flags_table np_login_timer_flags;
|
||||
u32 np_exports;
|
||||
enum np_flags_table np_flags;
|
||||
|
|
|
|||
|
|
@ -670,13 +670,14 @@ again:
|
|||
* this reference was taken by ihold under the page lock
|
||||
* pinning the inode in place so i_lock was unnecessary. The
|
||||
* only way for this check to fail is if the inode was
|
||||
* truncated in parallel so warn for now if this happens.
|
||||
* truncated in parallel which is almost certainly an
|
||||
* application bug. In such a case, just retry.
|
||||
*
|
||||
* We are not calling into get_futex_key_refs() in file-backed
|
||||
* cases, therefore a successful atomic_inc return below will
|
||||
* guarantee that get_futex_key() will still imply smp_mb(); (B).
|
||||
*/
|
||||
if (WARN_ON_ONCE(!atomic_inc_not_zero(&inode->i_count))) {
|
||||
if (!atomic_inc_not_zero(&inode->i_count)) {
|
||||
rcu_read_unlock();
|
||||
put_page(page);
|
||||
|
||||
|
|
|
|||
|
|
@ -7567,7 +7567,7 @@ int alloc_contig_range(unsigned long start, unsigned long end,
|
|||
|
||||
/* Make sure the range is really isolated. */
|
||||
if (test_pages_isolated(outer_start, end, false)) {
|
||||
pr_info("%s: [%lx, %lx) PFNs busy\n",
|
||||
pr_info_ratelimited("%s: [%lx, %lx) PFNs busy\n",
|
||||
__func__, outer_start, end);
|
||||
ret = -EBUSY;
|
||||
goto done;
|
||||
|
|
|
|||
12
mm/shmem.c
12
mm/shmem.c
|
|
@ -1021,7 +1021,11 @@ static int shmem_setattr(struct dentry *dentry, struct iattr *attr)
|
|||
*/
|
||||
if (IS_ENABLED(CONFIG_TRANSPARENT_HUGE_PAGECACHE)) {
|
||||
spin_lock(&sbinfo->shrinklist_lock);
|
||||
if (list_empty(&info->shrinklist)) {
|
||||
/*
|
||||
* _careful to defend against unlocked access to
|
||||
* ->shrink_list in shmem_unused_huge_shrink()
|
||||
*/
|
||||
if (list_empty_careful(&info->shrinklist)) {
|
||||
list_add_tail(&info->shrinklist,
|
||||
&sbinfo->shrinklist);
|
||||
sbinfo->shrinklist_len++;
|
||||
|
|
@ -1817,7 +1821,11 @@ alloc_nohuge: page = shmem_alloc_and_acct_page(gfp, info, sbinfo,
|
|||
* to shrink under memory pressure.
|
||||
*/
|
||||
spin_lock(&sbinfo->shrinklist_lock);
|
||||
if (list_empty(&info->shrinklist)) {
|
||||
/*
|
||||
* _careful to defend against unlocked access to
|
||||
* ->shrink_list in shmem_unused_huge_shrink()
|
||||
*/
|
||||
if (list_empty_careful(&info->shrinklist)) {
|
||||
list_add_tail(&info->shrinklist,
|
||||
&sbinfo->shrinklist);
|
||||
sbinfo->shrinklist_len++;
|
||||
|
|
|
|||
|
|
@ -2670,7 +2670,7 @@ static inline bool skb_needs_check(struct sk_buff *skb, bool tx_path)
|
|||
{
|
||||
if (tx_path)
|
||||
return skb->ip_summed != CHECKSUM_PARTIAL &&
|
||||
skb->ip_summed != CHECKSUM_NONE;
|
||||
skb->ip_summed != CHECKSUM_UNNECESSARY;
|
||||
|
||||
return skb->ip_summed == CHECKSUM_NONE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1731,6 +1731,13 @@ static __net_init int inet_init_net(struct net *net)
|
|||
net->ipv4.sysctl_ip_prot_sock = PROT_SOCK;
|
||||
#endif
|
||||
|
||||
/* Some igmp sysctl, whose values are always used */
|
||||
net->ipv4.sysctl_igmp_max_memberships = 20;
|
||||
net->ipv4.sysctl_igmp_max_msf = 10;
|
||||
/* IGMP reports for link-local multicast groups are enabled by default */
|
||||
net->ipv4.sysctl_igmp_llm_reports = 1;
|
||||
net->ipv4.sysctl_igmp_qrv = 2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2974,12 +2974,6 @@ static int __net_init igmp_net_init(struct net *net)
|
|||
goto out_sock;
|
||||
}
|
||||
|
||||
/* Sysctl initialization */
|
||||
net->ipv4.sysctl_igmp_max_memberships = 20;
|
||||
net->ipv4.sysctl_igmp_max_msf = 10;
|
||||
/* IGMP reports for link-local multicast groups are enabled by default */
|
||||
net->ipv4.sysctl_igmp_llm_reports = 1;
|
||||
net->ipv4.sysctl_igmp_qrv = 2;
|
||||
return 0;
|
||||
|
||||
out_sock:
|
||||
|
|
|
|||
|
|
@ -964,11 +964,12 @@ static int __ip_append_data(struct sock *sk,
|
|||
csummode = CHECKSUM_PARTIAL;
|
||||
|
||||
cork->length += length;
|
||||
if ((((length + (skb ? skb->len : fragheaderlen)) > mtu) ||
|
||||
(skb && skb_is_gso(skb))) &&
|
||||
if ((skb && skb_is_gso(skb)) ||
|
||||
(((length + (skb ? skb->len : fragheaderlen)) > mtu) &&
|
||||
(skb_queue_len(queue) <= 1) &&
|
||||
(sk->sk_protocol == IPPROTO_UDP) &&
|
||||
(rt->dst.dev->features & NETIF_F_UFO) && !dst_xfrm(&rt->dst) &&
|
||||
(sk->sk_type == SOCK_DGRAM) && !sk->sk_no_check_tx) {
|
||||
(sk->sk_type == SOCK_DGRAM) && !sk->sk_no_check_tx)) {
|
||||
err = ip_ufo_append_data(sk, queue, getfrag, from, length,
|
||||
hh_len, fragheaderlen, transhdrlen,
|
||||
maxfraglen, flags);
|
||||
|
|
@ -1287,6 +1288,7 @@ ssize_t ip_append_page(struct sock *sk, struct flowi4 *fl4, struct page *page,
|
|||
return -EINVAL;
|
||||
|
||||
if ((size + skb->len > mtu) &&
|
||||
(skb_queue_len(&sk->sk_write_queue) == 1) &&
|
||||
(sk->sk_protocol == IPPROTO_UDP) &&
|
||||
(rt->dst.dev->features & NETIF_F_UFO)) {
|
||||
if (skb->ip_summed != CHECKSUM_PARTIAL)
|
||||
|
|
|
|||
|
|
@ -2517,8 +2517,8 @@ static inline void tcp_end_cwnd_reduction(struct sock *sk)
|
|||
return;
|
||||
|
||||
/* Reset cwnd to ssthresh in CWR or Recovery (unless it's undone) */
|
||||
if (inet_csk(sk)->icsk_ca_state == TCP_CA_CWR ||
|
||||
(tp->undo_marker && tp->snd_ssthresh < TCP_INFINITE_SSTHRESH)) {
|
||||
if (tp->snd_ssthresh < TCP_INFINITE_SSTHRESH &&
|
||||
(inet_csk(sk)->icsk_ca_state == TCP_CA_CWR || tp->undo_marker)) {
|
||||
tp->snd_cwnd = tp->snd_ssthresh;
|
||||
tp->snd_cwnd_stamp = tcp_time_stamp;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3361,6 +3361,9 @@ int tcp_connect(struct sock *sk)
|
|||
struct sk_buff *buff;
|
||||
int err;
|
||||
|
||||
if (inet_csk(sk)->icsk_af_ops->rebuild_header(sk))
|
||||
return -EHOSTUNREACH; /* Routing failure or similar. */
|
||||
|
||||
tcp_connect_init(sk);
|
||||
|
||||
if (unlikely(tp->repair)) {
|
||||
|
|
|
|||
|
|
@ -654,7 +654,8 @@ static void tcp_keepalive_timer (unsigned long data)
|
|||
goto death;
|
||||
}
|
||||
|
||||
if (!sock_flag(sk, SOCK_KEEPOPEN) || sk->sk_state == TCP_CLOSE)
|
||||
if (!sock_flag(sk, SOCK_KEEPOPEN) ||
|
||||
((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_SYN_SENT)))
|
||||
goto out;
|
||||
|
||||
elapsed = keepalive_time_when(tp);
|
||||
|
|
|
|||
|
|
@ -802,7 +802,7 @@ static int udp_send_skb(struct sk_buff *skb, struct flowi4 *fl4)
|
|||
if (is_udplite) /* UDP-Lite */
|
||||
csum = udplite_csum(skb);
|
||||
|
||||
else if (sk->sk_no_check_tx) { /* UDP csum disabled */
|
||||
else if (sk->sk_no_check_tx && !skb_is_gso(skb)) { /* UDP csum off */
|
||||
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
goto send;
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ static struct sk_buff *udp4_ufo_fragment(struct sk_buff *skb,
|
|||
if (uh->check == 0)
|
||||
uh->check = CSUM_MANGLED_0;
|
||||
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
||||
|
||||
/* If there is no outer header we can fake a checksum offload
|
||||
* due to the fact that we have already done the checksum in
|
||||
|
|
|
|||
|
|
@ -1386,11 +1386,12 @@ emsgsize:
|
|||
*/
|
||||
|
||||
cork->length += length;
|
||||
if ((((length + (skb ? skb->len : headersize)) > mtu) ||
|
||||
(skb && skb_is_gso(skb))) &&
|
||||
if ((skb && skb_is_gso(skb)) ||
|
||||
(((length + (skb ? skb->len : headersize)) > mtu) &&
|
||||
(skb_queue_len(queue) <= 1) &&
|
||||
(sk->sk_protocol == IPPROTO_UDP) &&
|
||||
(rt->dst.dev->features & NETIF_F_UFO) && !dst_xfrm(&rt->dst) &&
|
||||
(sk->sk_type == SOCK_DGRAM) && !udp_get_no_check6_tx(sk)) {
|
||||
(sk->sk_type == SOCK_DGRAM) && !udp_get_no_check6_tx(sk))) {
|
||||
err = ip6_ufo_append_data(sk, queue, getfrag, from, length,
|
||||
hh_len, fragheaderlen, exthdrlen,
|
||||
transhdrlen, mtu, flags, fl6);
|
||||
|
|
|
|||
|
|
@ -2366,6 +2366,7 @@ static void rt6_do_redirect(struct dst_entry *dst, struct sock *sk, struct sk_bu
|
|||
if (on_link)
|
||||
nrt->rt6i_flags &= ~RTF_GATEWAY;
|
||||
|
||||
nrt->rt6i_protocol = RTPROT_REDIRECT;
|
||||
nrt->rt6i_gateway = *(struct in6_addr *)neigh->primary_key;
|
||||
|
||||
if (ip6_ins_rt(nrt))
|
||||
|
|
@ -2470,6 +2471,7 @@ static struct rt6_info *rt6_add_route_info(struct net *net,
|
|||
.fc_dst_len = prefixlen,
|
||||
.fc_flags = RTF_GATEWAY | RTF_ADDRCONF | RTF_ROUTEINFO |
|
||||
RTF_UP | RTF_PREF(pref),
|
||||
.fc_protocol = RTPROT_RA,
|
||||
.fc_nlinfo.portid = 0,
|
||||
.fc_nlinfo.nlh = NULL,
|
||||
.fc_nlinfo.nl_net = net,
|
||||
|
|
@ -2522,6 +2524,7 @@ struct rt6_info *rt6_add_dflt_router(const struct in6_addr *gwaddr,
|
|||
.fc_ifindex = dev->ifindex,
|
||||
.fc_flags = RTF_GATEWAY | RTF_ADDRCONF | RTF_DEFAULT |
|
||||
RTF_UP | RTF_EXPIRES | RTF_PREF(pref),
|
||||
.fc_protocol = RTPROT_RA,
|
||||
.fc_nlinfo.portid = 0,
|
||||
.fc_nlinfo.nlh = NULL,
|
||||
.fc_nlinfo.nl_net = dev_net(dev),
|
||||
|
|
@ -3434,14 +3437,6 @@ static int rt6_fill_node(struct net *net,
|
|||
rtm->rtm_flags = 0;
|
||||
rtm->rtm_scope = RT_SCOPE_UNIVERSE;
|
||||
rtm->rtm_protocol = rt->rt6i_protocol;
|
||||
if (rt->rt6i_flags & RTF_DYNAMIC)
|
||||
rtm->rtm_protocol = RTPROT_REDIRECT;
|
||||
else if (rt->rt6i_flags & RTF_ADDRCONF) {
|
||||
if (rt->rt6i_flags & (RTF_DEFAULT | RTF_ROUTEINFO))
|
||||
rtm->rtm_protocol = RTPROT_RA;
|
||||
else
|
||||
rtm->rtm_protocol = RTPROT_KERNEL;
|
||||
}
|
||||
|
||||
if (rt->rt6i_flags & RTF_CACHE)
|
||||
rtm->rtm_flags |= RTM_F_CLONED;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static struct sk_buff *udp6_ufo_fragment(struct sk_buff *skb,
|
|||
if (uh->check == 0)
|
||||
uh->check = CSUM_MANGLED_0;
|
||||
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
||||
|
||||
/* If there is no outer header we can fake a checksum offload
|
||||
* due to the fact that we have already done the checksum in
|
||||
|
|
|
|||
|
|
@ -3705,14 +3705,19 @@ packet_setsockopt(struct socket *sock, int level, int optname, char __user *optv
|
|||
|
||||
if (optlen != sizeof(val))
|
||||
return -EINVAL;
|
||||
if (po->rx_ring.pg_vec || po->tx_ring.pg_vec)
|
||||
return -EBUSY;
|
||||
if (copy_from_user(&val, optval, sizeof(val)))
|
||||
return -EFAULT;
|
||||
if (val > INT_MAX)
|
||||
return -EINVAL;
|
||||
po->tp_reserve = val;
|
||||
return 0;
|
||||
lock_sock(sk);
|
||||
if (po->rx_ring.pg_vec || po->tx_ring.pg_vec) {
|
||||
ret = -EBUSY;
|
||||
} else {
|
||||
po->tp_reserve = val;
|
||||
ret = 0;
|
||||
}
|
||||
release_sock(sk);
|
||||
return ret;
|
||||
}
|
||||
case PACKET_LOSS:
|
||||
{
|
||||
|
|
|
|||
|
|
@ -36,8 +36,8 @@ static struct tc_action_ops act_ipt_ops;
|
|||
static unsigned int xt_net_id;
|
||||
static struct tc_action_ops act_xt_ops;
|
||||
|
||||
static int ipt_init_target(struct xt_entry_target *t, char *table,
|
||||
unsigned int hook)
|
||||
static int ipt_init_target(struct net *net, struct xt_entry_target *t,
|
||||
char *table, unsigned int hook)
|
||||
{
|
||||
struct xt_tgchk_param par;
|
||||
struct xt_target *target;
|
||||
|
|
@ -49,8 +49,9 @@ static int ipt_init_target(struct xt_entry_target *t, char *table,
|
|||
return PTR_ERR(target);
|
||||
|
||||
t->u.kernel.target = target;
|
||||
memset(&par, 0, sizeof(par));
|
||||
par.net = net;
|
||||
par.table = table;
|
||||
par.entryinfo = NULL;
|
||||
par.target = target;
|
||||
par.targinfo = t->data;
|
||||
par.hook_mask = hook;
|
||||
|
|
@ -91,10 +92,11 @@ static const struct nla_policy ipt_policy[TCA_IPT_MAX + 1] = {
|
|||
[TCA_IPT_TARG] = { .len = sizeof(struct xt_entry_target) },
|
||||
};
|
||||
|
||||
static int __tcf_ipt_init(struct tc_action_net *tn, struct nlattr *nla,
|
||||
static int __tcf_ipt_init(struct net *net, unsigned int id, struct nlattr *nla,
|
||||
struct nlattr *est, struct tc_action **a,
|
||||
const struct tc_action_ops *ops, int ovr, int bind)
|
||||
{
|
||||
struct tc_action_net *tn = net_generic(net, id);
|
||||
struct nlattr *tb[TCA_IPT_MAX + 1];
|
||||
struct tcf_ipt *ipt;
|
||||
struct xt_entry_target *td, *t;
|
||||
|
|
@ -159,7 +161,7 @@ static int __tcf_ipt_init(struct tc_action_net *tn, struct nlattr *nla,
|
|||
if (unlikely(!t))
|
||||
goto err2;
|
||||
|
||||
err = ipt_init_target(t, tname, hook);
|
||||
err = ipt_init_target(net, t, tname, hook);
|
||||
if (err < 0)
|
||||
goto err3;
|
||||
|
||||
|
|
@ -193,18 +195,16 @@ static int tcf_ipt_init(struct net *net, struct nlattr *nla,
|
|||
struct nlattr *est, struct tc_action **a, int ovr,
|
||||
int bind)
|
||||
{
|
||||
struct tc_action_net *tn = net_generic(net, ipt_net_id);
|
||||
|
||||
return __tcf_ipt_init(tn, nla, est, a, &act_ipt_ops, ovr, bind);
|
||||
return __tcf_ipt_init(net, ipt_net_id, nla, est, a, &act_ipt_ops, ovr,
|
||||
bind);
|
||||
}
|
||||
|
||||
static int tcf_xt_init(struct net *net, struct nlattr *nla,
|
||||
struct nlattr *est, struct tc_action **a, int ovr,
|
||||
int bind)
|
||||
{
|
||||
struct tc_action_net *tn = net_generic(net, xt_net_id);
|
||||
|
||||
return __tcf_ipt_init(tn, nla, est, a, &act_xt_ops, ovr, bind);
|
||||
return __tcf_ipt_init(net, xt_net_id, nla, est, a, &act_xt_ops, ovr,
|
||||
bind);
|
||||
}
|
||||
|
||||
static int tcf_ipt(struct sk_buff *skb, const struct tc_action *a,
|
||||
|
|
|
|||
Loading…
Reference in a new issue