2017-08-10 13:25:24 +00:00
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/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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2017-09-05 02:31:27 +00:00
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*
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2017-08-10 13:25:24 +00:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2017-09-05 02:31:27 +00:00
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*
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2017-08-10 13:25:24 +00:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2017-09-05 02:31:27 +00:00
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*
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2017-08-10 13:25:24 +00:00
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/semaphore.h>
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#include <crypto/algapi.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/aes.h>
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#include <crypto/ctr.h>
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#include <crypto/des.h>
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2017-10-03 17:33:45 +00:00
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#include <crypto/xts.h>
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2017-09-10 12:49:22 +00:00
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#include <crypto/scatterwalk.h>
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2017-08-10 13:25:24 +00:00
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#include "ssi_config.h"
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#include "ssi_driver.h"
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#include "cc_lli_defs.h"
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#include "ssi_buffer_mgr.h"
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#include "ssi_cipher.h"
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#include "ssi_request_mgr.h"
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#include "ssi_sysfs.h"
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#define MAX_ABLKCIPHER_SEQ_LEN 6
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#define template_ablkcipher template_u.ablkcipher
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#define SSI_MIN_AES_XTS_SIZE 0x10
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#define SSI_MAX_AES_XTS_SIZE 0x2000
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struct ssi_blkcipher_handle {
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struct list_head blkcipher_alg_list;
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};
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struct cc_user_key_info {
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2017-09-05 02:31:27 +00:00
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u8 *key;
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2017-08-10 13:25:24 +00:00
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dma_addr_t key_dma_addr;
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};
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2017-09-05 02:31:27 +00:00
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2017-08-10 13:25:24 +00:00
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struct cc_hw_key_info {
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2017-09-05 02:31:27 +00:00
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enum cc_hw_crypto_key key1_slot;
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enum cc_hw_crypto_key key2_slot;
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2017-08-10 13:25:24 +00:00
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};
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struct ssi_ablkcipher_ctx {
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struct ssi_drvdata *drvdata;
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int keylen;
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int key_round_number;
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int cipher_mode;
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int flow_mode;
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unsigned int flags;
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struct blkcipher_req_ctx *sync_ctx;
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struct cc_user_key_info user;
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struct cc_hw_key_info hw;
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struct crypto_shash *shash_tfm;
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};
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static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __iomem *cc_base);
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2017-10-03 17:33:45 +00:00
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static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size)
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{
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2017-09-05 02:31:27 +00:00
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switch (ctx_p->flow_mode) {
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2017-08-10 13:25:24 +00:00
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case S_DIN_to_AES:
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2017-09-05 02:31:27 +00:00
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switch (size) {
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2017-08-10 13:25:24 +00:00
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case CC_AES_128_BIT_KEY_SIZE:
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case CC_AES_192_BIT_KEY_SIZE:
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if (likely((ctx_p->cipher_mode != DRV_CIPHER_XTS) &&
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(ctx_p->cipher_mode != DRV_CIPHER_ESSIV) &&
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(ctx_p->cipher_mode != DRV_CIPHER_BITLOCKER)))
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return 0;
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break;
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case CC_AES_256_BIT_KEY_SIZE:
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return 0;
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2017-09-05 02:31:27 +00:00
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case (CC_AES_192_BIT_KEY_SIZE * 2):
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case (CC_AES_256_BIT_KEY_SIZE * 2):
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2017-08-10 13:25:24 +00:00
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if (likely((ctx_p->cipher_mode == DRV_CIPHER_XTS) ||
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(ctx_p->cipher_mode == DRV_CIPHER_ESSIV) ||
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(ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)))
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return 0;
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break;
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default:
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break;
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}
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case S_DIN_to_DES:
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2017-10-03 17:33:45 +00:00
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if (likely(size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE))
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2017-08-10 13:25:24 +00:00
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return 0;
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break;
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#if SSI_CC_HAS_MULTI2
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case S_DIN_to_MULTI2:
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if (likely(size == CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE))
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return 0;
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break;
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#endif
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default:
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break;
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}
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return -EINVAL;
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}
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2017-10-03 17:33:45 +00:00
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static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int size)
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{
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2017-09-05 02:31:27 +00:00
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switch (ctx_p->flow_mode) {
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2017-08-10 13:25:24 +00:00
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case S_DIN_to_AES:
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2017-09-05 02:31:27 +00:00
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switch (ctx_p->cipher_mode) {
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2017-08-10 13:25:24 +00:00
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case DRV_CIPHER_XTS:
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if ((size >= SSI_MIN_AES_XTS_SIZE) &&
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2017-09-05 02:31:27 +00:00
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(size <= SSI_MAX_AES_XTS_SIZE) &&
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2017-08-10 13:25:24 +00:00
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IS_ALIGNED(size, AES_BLOCK_SIZE))
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return 0;
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break;
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case DRV_CIPHER_CBC_CTS:
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if (likely(size >= AES_BLOCK_SIZE))
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return 0;
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break;
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case DRV_CIPHER_OFB:
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case DRV_CIPHER_CTR:
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return 0;
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case DRV_CIPHER_ECB:
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case DRV_CIPHER_CBC:
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case DRV_CIPHER_ESSIV:
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case DRV_CIPHER_BITLOCKER:
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if (likely(IS_ALIGNED(size, AES_BLOCK_SIZE)))
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return 0;
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break;
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default:
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break;
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}
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break;
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case S_DIN_to_DES:
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if (likely(IS_ALIGNED(size, DES_BLOCK_SIZE)))
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return 0;
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break;
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#if SSI_CC_HAS_MULTI2
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case S_DIN_to_MULTI2:
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switch (ctx_p->cipher_mode) {
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case DRV_MULTI2_CBC:
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if (likely(IS_ALIGNED(size, CC_MULTI2_BLOCK_SIZE)))
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return 0;
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break;
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case DRV_MULTI2_OFB:
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return 0;
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default:
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break;
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}
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break;
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#endif /*SSI_CC_HAS_MULTI2*/
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default:
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break;
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}
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return -EINVAL;
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}
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static unsigned int get_max_keysize(struct crypto_tfm *tfm)
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{
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struct ssi_crypto_alg *ssi_alg = container_of(tfm->__crt_alg, struct ssi_crypto_alg, crypto_alg);
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2017-09-05 02:31:27 +00:00
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if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_ABLKCIPHER)
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2017-08-10 13:25:24 +00:00
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return ssi_alg->crypto_alg.cra_ablkcipher.max_keysize;
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2017-09-05 02:31:27 +00:00
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if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER)
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2017-08-10 13:25:24 +00:00
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return ssi_alg->crypto_alg.cra_blkcipher.max_keysize;
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return 0;
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}
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static int ssi_blkcipher_init(struct crypto_tfm *tfm)
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{
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struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
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struct crypto_alg *alg = tfm->__crt_alg;
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struct ssi_crypto_alg *ssi_alg =
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container_of(alg, struct ssi_crypto_alg, crypto_alg);
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struct device *dev;
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int rc = 0;
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unsigned int max_key_buf_size = get_max_keysize(tfm);
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2017-10-03 17:33:45 +00:00
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SSI_LOG_DEBUG("Initializing context @%p for %s\n",
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ctx_p, crypto_tfm_alg_name(tfm));
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2017-08-10 13:25:24 +00:00
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ctx_p->cipher_mode = ssi_alg->cipher_mode;
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ctx_p->flow_mode = ssi_alg->flow_mode;
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ctx_p->drvdata = ssi_alg->drvdata;
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dev = &ctx_p->drvdata->plat_dev->dev;
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/* Allocate key buffer, cache line aligned */
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2017-09-05 02:31:27 +00:00
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ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA);
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2017-08-10 13:25:24 +00:00
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if (!ctx_p->user.key) {
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SSI_LOG_ERR("Allocating key buffer in context failed\n");
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rc = -ENOMEM;
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}
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SSI_LOG_DEBUG("Allocated key buffer in context. key=@%p\n",
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ctx_p->user.key);
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/* Map key buffer */
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ctx_p->user.key_dma_addr = dma_map_single(dev, (void *)ctx_p->user.key,
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2017-10-03 17:33:45 +00:00
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max_key_buf_size,
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DMA_TO_DEVICE);
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2017-08-10 13:25:24 +00:00
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if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) {
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SSI_LOG_ERR("Mapping Key %u B at va=%pK for DMA failed\n",
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2017-10-03 17:33:45 +00:00
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max_key_buf_size, ctx_p->user.key);
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2017-08-10 13:25:24 +00:00
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return -ENOMEM;
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}
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2017-10-03 17:33:45 +00:00
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SSI_LOG_DEBUG("Mapped key %u B at va=%pK to dma=%pad\n",
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max_key_buf_size, ctx_p->user.key,
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ctx_p->user.key_dma_addr);
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2017-08-10 13:25:24 +00:00
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if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
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/* Alloc hash tfm for essiv */
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ctx_p->shash_tfm = crypto_alloc_shash("sha256-generic", 0, 0);
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if (IS_ERR(ctx_p->shash_tfm)) {
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SSI_LOG_ERR("Error allocating hash tfm for ESSIV.\n");
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return PTR_ERR(ctx_p->shash_tfm);
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}
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}
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return rc;
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}
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static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
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{
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struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
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struct device *dev = &ctx_p->drvdata->plat_dev->dev;
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unsigned int max_key_buf_size = get_max_keysize(tfm);
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SSI_LOG_DEBUG("Clearing context @%p for %s\n",
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2017-10-03 17:33:45 +00:00
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crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm));
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2017-08-10 13:25:24 +00:00
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if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
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/* Free hash tfm for essiv */
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crypto_free_shash(ctx_p->shash_tfm);
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ctx_p->shash_tfm = NULL;
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}
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/* Unmap key buffer */
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dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size,
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2017-10-03 17:33:45 +00:00
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DMA_TO_DEVICE);
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SSI_LOG_DEBUG("Unmapped key buffer key_dma_addr=%pad\n",
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ctx_p->user.key_dma_addr);
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2017-08-10 13:25:24 +00:00
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/* Free key buffer in context */
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kfree(ctx_p->user.key);
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SSI_LOG_DEBUG("Free key buffer in context. key=@%p\n", ctx_p->user.key);
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}
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2017-09-05 02:31:27 +00:00
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struct tdes_keys {
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u8 key1[DES_KEY_SIZE];
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u8 key2[DES_KEY_SIZE];
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u8 key3[DES_KEY_SIZE];
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};
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2017-08-10 13:25:24 +00:00
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2017-09-05 02:31:27 +00:00
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static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
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2017-08-10 13:25:24 +00:00
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/* The function verifies that tdes keys are not weak.*/
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2017-10-03 17:33:45 +00:00
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static int ssi_verify_3des_keys(const u8 *key, unsigned int keylen)
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2017-08-10 13:25:24 +00:00
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{
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2017-09-05 02:31:27 +00:00
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struct tdes_keys *tdes_key = (struct tdes_keys *)key;
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2017-08-10 13:25:24 +00:00
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/* verify key1 != key2 and key3 != key2*/
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2017-09-05 02:31:27 +00:00
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if (unlikely((memcmp((u8 *)tdes_key->key1, (u8 *)tdes_key->key2, sizeof(tdes_key->key1)) == 0) ||
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2017-10-03 17:33:45 +00:00
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(memcmp((u8 *)tdes_key->key3, (u8 *)tdes_key->key2, sizeof(tdes_key->key3)) == 0))) {
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2017-09-05 02:31:27 +00:00
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return -ENOEXEC;
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}
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2017-08-10 13:25:24 +00:00
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2017-09-05 02:31:27 +00:00
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return 0;
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2017-08-10 13:25:24 +00:00
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}
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2017-09-05 02:31:27 +00:00
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static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
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2017-08-10 13:25:24 +00:00
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{
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switch (slot_num) {
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case 0:
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return KFDE0_KEY;
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case 1:
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return KFDE1_KEY;
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case 2:
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return KFDE2_KEY;
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case 3:
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return KFDE3_KEY;
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}
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return END_OF_KEYS;
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}
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2017-09-05 02:31:27 +00:00
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static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
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const u8 *key,
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2017-08-10 13:25:24 +00:00
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unsigned int keylen)
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{
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struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
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|
|
struct device *dev = &ctx_p->drvdata->plat_dev->dev;
|
|
|
|
u32 tmp[DES_EXPKEY_WORDS];
|
|
|
|
unsigned int max_key_buf_size = get_max_keysize(tfm);
|
|
|
|
|
|
|
|
SSI_LOG_DEBUG("Setting key in context @%p for %s. keylen=%u\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
ctx_p, crypto_tfm_alg_name(tfm), keylen);
|
2017-09-05 02:31:27 +00:00
|
|
|
dump_byte_array("key", (u8 *)key, keylen);
|
2017-08-10 13:25:24 +00:00
|
|
|
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG("after FIPS check");
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
/* STAT_PHASE_0: Init and sanity checks */
|
|
|
|
|
|
|
|
#if SSI_CC_HAS_MULTI2
|
|
|
|
/*last byte of key buffer is round number and should not be a part of key size*/
|
2017-09-05 02:31:27 +00:00
|
|
|
if (ctx_p->flow_mode == S_DIN_to_MULTI2)
|
|
|
|
keylen -= 1;
|
2017-08-10 13:25:24 +00:00
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) {
|
2017-08-10 13:25:24 +00:00
|
|
|
SSI_LOG_ERR("Unsupported key size %d.\n", keylen);
|
|
|
|
crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ssi_is_hw_key(tfm)) {
|
|
|
|
/* setting HW key slots */
|
2017-09-05 02:31:27 +00:00
|
|
|
struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key;
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
if (unlikely(ctx_p->flow_mode != S_DIN_to_AES)) {
|
|
|
|
SSI_LOG_ERR("HW key not supported for non-AES flows\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx_p->hw.key1_slot = hw_key_to_cc_hw_key(hki->hw_key1);
|
|
|
|
if (unlikely(ctx_p->hw.key1_slot == END_OF_KEYS)) {
|
|
|
|
SSI_LOG_ERR("Unsupported hw key1 number (%d)\n", hki->hw_key1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) ||
|
|
|
|
(ctx_p->cipher_mode == DRV_CIPHER_ESSIV) ||
|
|
|
|
(ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)) {
|
|
|
|
if (unlikely(hki->hw_key1 == hki->hw_key2)) {
|
|
|
|
SSI_LOG_ERR("Illegal hw key numbers (%d,%d)\n", hki->hw_key1, hki->hw_key2);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
ctx_p->hw.key2_slot = hw_key_to_cc_hw_key(hki->hw_key2);
|
|
|
|
if (unlikely(ctx_p->hw.key2_slot == END_OF_KEYS)) {
|
|
|
|
SSI_LOG_ERR("Unsupported hw key2 number (%d)\n", hki->hw_key2);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx_p->keylen = keylen;
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG("ssi_is_hw_key ret 0");
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// verify weak keys
|
|
|
|
if (ctx_p->flow_mode == S_DIN_to_DES) {
|
|
|
|
if (unlikely(!des_ekey(tmp, key)) &&
|
|
|
|
(crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) {
|
|
|
|
tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG("weak DES key");
|
2017-08-10 13:25:24 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) &&
|
2017-10-03 17:33:45 +00:00
|
|
|
xts_check_key(tfm, key, keylen) != 0) {
|
|
|
|
SSI_LOG_DEBUG("weak XTS key");
|
2017-08-10 13:25:24 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
if ((ctx_p->flow_mode == S_DIN_to_DES) &&
|
|
|
|
(keylen == DES3_EDE_KEY_SIZE) &&
|
2017-10-03 17:33:45 +00:00
|
|
|
ssi_verify_3des_keys(key, keylen) != 0) {
|
|
|
|
SSI_LOG_DEBUG("weak 3DES key");
|
2017-08-10 13:25:24 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* STAT_PHASE_1: Copy key to ctx */
|
2017-09-05 02:31:27 +00:00
|
|
|
dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr,
|
2017-10-03 17:33:45 +00:00
|
|
|
max_key_buf_size, DMA_TO_DEVICE);
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
if (ctx_p->flow_mode == S_DIN_to_MULTI2) {
|
2017-09-05 02:31:27 +00:00
|
|
|
#if SSI_CC_HAS_MULTI2
|
2017-08-10 13:25:24 +00:00
|
|
|
memcpy(ctx_p->user.key, key, CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE);
|
|
|
|
ctx_p->key_round_number = key[CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE];
|
|
|
|
if (ctx_p->key_round_number < CC_MULTI2_MIN_NUM_ROUNDS ||
|
|
|
|
ctx_p->key_round_number > CC_MULTI2_MAX_NUM_ROUNDS) {
|
|
|
|
crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG("SSI_CC_HAS_MULTI2 einval");
|
2017-08-10 13:25:24 +00:00
|
|
|
return -EINVAL;
|
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
2017-09-05 02:31:27 +00:00
|
|
|
} else {
|
2017-08-10 13:25:24 +00:00
|
|
|
memcpy(ctx_p->user.key, key, keylen);
|
|
|
|
if (keylen == 24)
|
|
|
|
memset(ctx_p->user.key + 24, 0, CC_AES_KEY_SIZE_MAX - 24);
|
|
|
|
|
|
|
|
if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
|
|
|
|
/* sha256 for key2 - use sw implementation */
|
|
|
|
int key_len = keylen >> 1;
|
|
|
|
int err;
|
|
|
|
SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm);
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
desc->tfm = ctx_p->shash_tfm;
|
|
|
|
|
|
|
|
err = crypto_shash_digest(desc, ctx_p->user.key, key_len, ctx_p->user.key + key_len);
|
|
|
|
if (err) {
|
|
|
|
SSI_LOG_ERR("Failed to hash ESSIV key.\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr,
|
2017-10-03 17:33:45 +00:00
|
|
|
max_key_buf_size, DMA_TO_DEVICE);
|
2017-08-10 13:25:24 +00:00
|
|
|
ctx_p->keylen = keylen;
|
|
|
|
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG("return safely");
|
2017-08-10 13:25:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
ssi_blkcipher_create_setup_desc(
|
|
|
|
struct crypto_tfm *tfm,
|
|
|
|
struct blkcipher_req_ctx *req_ctx,
|
|
|
|
unsigned int ivsize,
|
|
|
|
unsigned int nbytes,
|
2017-09-05 02:31:27 +00:00
|
|
|
struct cc_hw_desc desc[],
|
2017-08-10 13:25:24 +00:00
|
|
|
unsigned int *seq_size)
|
|
|
|
{
|
|
|
|
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
|
|
|
|
int cipher_mode = ctx_p->cipher_mode;
|
|
|
|
int flow_mode = ctx_p->flow_mode;
|
|
|
|
int direction = req_ctx->gen_ctx.op_type;
|
|
|
|
dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
|
|
|
|
unsigned int key_len = ctx_p->keylen;
|
|
|
|
dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
|
|
|
|
unsigned int du_size = nbytes;
|
|
|
|
|
|
|
|
struct ssi_crypto_alg *ssi_alg = container_of(tfm->__crt_alg, struct ssi_crypto_alg, crypto_alg);
|
|
|
|
|
|
|
|
if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == CRYPTO_ALG_BULK_DU_512)
|
|
|
|
du_size = 512;
|
|
|
|
if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == CRYPTO_ALG_BULK_DU_4096)
|
|
|
|
du_size = 4096;
|
|
|
|
|
|
|
|
switch (cipher_mode) {
|
|
|
|
case DRV_CIPHER_CBC:
|
|
|
|
case DRV_CIPHER_CBC_CTS:
|
|
|
|
case DRV_CIPHER_CTR:
|
|
|
|
case DRV_CIPHER_OFB:
|
|
|
|
/* Load cipher state */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,
|
|
|
|
NS_BIT);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
|
|
|
set_cipher_mode(&desc[*seq_size], cipher_mode);
|
|
|
|
if ((cipher_mode == DRV_CIPHER_CTR) ||
|
|
|
|
(cipher_mode == DRV_CIPHER_OFB)) {
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
|
|
|
(*seq_size)++;
|
|
|
|
/*FALLTHROUGH*/
|
|
|
|
case DRV_CIPHER_ECB:
|
|
|
|
/* Load key */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_cipher_mode(&desc[*seq_size], cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (flow_mode == S_DIN_to_AES) {
|
|
|
|
if (ssi_is_hw_key(tfm)) {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_hw_crypto_key(&desc[*seq_size],
|
|
|
|
ctx_p->hw.key1_slot);
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI,
|
|
|
|
key_dma_addr, ((key_len == 24) ?
|
|
|
|
AES_MAX_KEY_SIZE :
|
|
|
|
key_len), NS_BIT);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
set_key_size_aes(&desc[*seq_size], key_len);
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
|
|
|
/*des*/
|
2017-09-05 02:31:27 +00:00
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
|
|
|
|
key_len, NS_BIT);
|
|
|
|
set_key_size_des(&desc[*seq_size], key_len);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
break;
|
|
|
|
case DRV_CIPHER_XTS:
|
|
|
|
case DRV_CIPHER_ESSIV:
|
|
|
|
case DRV_CIPHER_BITLOCKER:
|
|
|
|
/* Load AES key */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_cipher_mode(&desc[*seq_size], cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (ssi_is_hw_key(tfm)) {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_hw_crypto_key(&desc[*seq_size],
|
|
|
|
ctx_p->hw.key1_slot);
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
|
|
|
|
(key_len / 2), NS_BIT);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
set_key_size_aes(&desc[*seq_size], (key_len / 2));
|
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
|
|
|
|
/* load XEX key */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_cipher_mode(&desc[*seq_size], cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (ssi_is_hw_key(tfm)) {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_hw_crypto_key(&desc[*seq_size],
|
|
|
|
ctx_p->hw.key2_slot);
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI,
|
|
|
|
(key_dma_addr + (key_len / 2)),
|
|
|
|
(key_len / 2), NS_BIT);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
set_xex_data_unit_size(&desc[*seq_size], du_size);
|
|
|
|
set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);
|
|
|
|
set_key_size_aes(&desc[*seq_size], (key_len / 2));
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
/* Set state */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
|
|
|
|
set_cipher_mode(&desc[*seq_size], cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
|
|
|
set_key_size_aes(&desc[*seq_size], (key_len / 2));
|
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,
|
|
|
|
CC_AES_BLOCK_SIZE, NS_BIT);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
SSI_LOG_ERR("Unsupported cipher mode (%d)\n", cipher_mode);
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if SSI_CC_HAS_MULTI2
|
|
|
|
static inline void ssi_blkcipher_create_multi2_setup_desc(
|
|
|
|
struct crypto_tfm *tfm,
|
|
|
|
struct blkcipher_req_ctx *req_ctx,
|
|
|
|
unsigned int ivsize,
|
2017-09-05 02:31:27 +00:00
|
|
|
struct cc_hw_desc desc[],
|
2017-08-10 13:25:24 +00:00
|
|
|
unsigned int *seq_size)
|
|
|
|
{
|
|
|
|
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
int direction = req_ctx->gen_ctx.op_type;
|
|
|
|
/* Load system key */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, ctx_p->user.key_dma_addr,
|
|
|
|
CC_MULTI2_SYSTEM_KEY_SIZE, NS_BIT);
|
|
|
|
set_flow_mode(&desc[*seq_size], ctx_p->flow_mode);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
|
|
|
|
/* load data key */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI,
|
|
|
|
(ctx_p->user.key_dma_addr + CC_MULTI2_SYSTEM_KEY_SIZE),
|
|
|
|
CC_MULTI2_DATA_KEY_SIZE, NS_BIT);
|
|
|
|
set_multi2_num_rounds(&desc[*seq_size], ctx_p->key_round_number);
|
|
|
|
set_flow_mode(&desc[*seq_size], ctx_p->flow_mode);
|
|
|
|
set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
/* Set state */
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, req_ctx->gen_ctx.iv_dma_addr,
|
|
|
|
ivsize, NS_BIT);
|
|
|
|
set_cipher_config0(&desc[*seq_size], direction);
|
|
|
|
set_flow_mode(&desc[*seq_size], ctx_p->flow_mode);
|
|
|
|
set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode);
|
|
|
|
set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
}
|
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
ssi_blkcipher_create_data_desc(
|
|
|
|
struct crypto_tfm *tfm,
|
|
|
|
struct blkcipher_req_ctx *req_ctx,
|
|
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
|
|
unsigned int nbytes,
|
|
|
|
void *areq,
|
2017-09-05 02:31:27 +00:00
|
|
|
struct cc_hw_desc desc[],
|
2017-08-10 13:25:24 +00:00
|
|
|
unsigned int *seq_size)
|
|
|
|
{
|
|
|
|
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
|
|
|
|
unsigned int flow_mode = ctx_p->flow_mode;
|
|
|
|
|
|
|
|
switch (ctx_p->flow_mode) {
|
|
|
|
case S_DIN_to_AES:
|
|
|
|
flow_mode = DIN_AES_DOUT;
|
|
|
|
break;
|
|
|
|
case S_DIN_to_DES:
|
|
|
|
flow_mode = DIN_DES_DOUT;
|
|
|
|
break;
|
|
|
|
#if SSI_CC_HAS_MULTI2
|
|
|
|
case S_DIN_to_MULTI2:
|
|
|
|
flow_mode = DIN_MULTI2_DOUT;
|
|
|
|
break;
|
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
|
|
|
default:
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_ERR("invalid flow mode, flow_mode = %d\n", flow_mode);
|
2017-08-10 13:25:24 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* Process */
|
2017-09-05 02:31:27 +00:00
|
|
|
if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) {
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n",
|
|
|
|
sg_dma_address(src), nbytes);
|
|
|
|
SSI_LOG_DEBUG(" data params addr %pad length 0x%X\n",
|
|
|
|
sg_dma_address(dst), nbytes);
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),
|
|
|
|
nbytes, NS_BIT);
|
|
|
|
set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),
|
|
|
|
nbytes, NS_BIT, (!areq ? 0 : 1));
|
|
|
|
if (areq)
|
|
|
|
set_queue_last_ind(&desc[*seq_size]);
|
|
|
|
|
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
} else {
|
|
|
|
/* bypass */
|
2017-10-03 17:33:45 +00:00
|
|
|
SSI_LOG_DEBUG(" bypass params addr %pad "
|
2017-08-10 13:25:24 +00:00
|
|
|
"length 0x%X addr 0x%08X\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
req_ctx->mlli_params.mlli_dma_addr,
|
2017-08-10 13:25:24 +00:00
|
|
|
req_ctx->mlli_params.mlli_len,
|
|
|
|
(unsigned int)ctx_p->drvdata->mlli_sram_addr);
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_DLLI,
|
|
|
|
req_ctx->mlli_params.mlli_dma_addr,
|
|
|
|
req_ctx->mlli_params.mlli_len, NS_BIT);
|
|
|
|
set_dout_sram(&desc[*seq_size],
|
|
|
|
ctx_p->drvdata->mlli_sram_addr,
|
|
|
|
req_ctx->mlli_params.mlli_len);
|
|
|
|
set_flow_mode(&desc[*seq_size], BYPASS);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
hw_desc_init(&desc[*seq_size]);
|
|
|
|
set_din_type(&desc[*seq_size], DMA_MLLI,
|
|
|
|
ctx_p->drvdata->mlli_sram_addr,
|
|
|
|
req_ctx->in_mlli_nents, NS_BIT);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (req_ctx->out_nents == 0) {
|
|
|
|
SSI_LOG_DEBUG(" din/dout params addr 0x%08X "
|
|
|
|
"addr 0x%08X\n",
|
|
|
|
(unsigned int)ctx_p->drvdata->mlli_sram_addr,
|
|
|
|
(unsigned int)ctx_p->drvdata->mlli_sram_addr);
|
2017-09-05 02:31:27 +00:00
|
|
|
set_dout_mlli(&desc[*seq_size],
|
|
|
|
ctx_p->drvdata->mlli_sram_addr,
|
|
|
|
req_ctx->in_mlli_nents, NS_BIT,
|
|
|
|
(!areq ? 0 : 1));
|
2017-08-10 13:25:24 +00:00
|
|
|
} else {
|
|
|
|
SSI_LOG_DEBUG(" din/dout params "
|
|
|
|
"addr 0x%08X addr 0x%08X\n",
|
|
|
|
(unsigned int)ctx_p->drvdata->mlli_sram_addr,
|
2017-09-05 02:31:27 +00:00
|
|
|
(unsigned int)ctx_p->drvdata->mlli_sram_addr +
|
|
|
|
(u32)LLI_ENTRY_BYTE_SIZE *
|
2017-08-10 13:25:24 +00:00
|
|
|
req_ctx->in_nents);
|
2017-09-05 02:31:27 +00:00
|
|
|
set_dout_mlli(&desc[*seq_size],
|
|
|
|
(ctx_p->drvdata->mlli_sram_addr +
|
|
|
|
(LLI_ENTRY_BYTE_SIZE *
|
|
|
|
req_ctx->in_mlli_nents)),
|
|
|
|
req_ctx->out_mlli_nents, NS_BIT,
|
|
|
|
(!areq ? 0 : 1));
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
if (areq)
|
|
|
|
set_queue_last_ind(&desc[*seq_size]);
|
|
|
|
|
|
|
|
set_flow_mode(&desc[*seq_size], flow_mode);
|
2017-08-10 13:25:24 +00:00
|
|
|
(*seq_size)++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ssi_blkcipher_complete(struct device *dev,
|
2017-10-03 17:33:45 +00:00
|
|
|
struct ssi_ablkcipher_ctx *ctx_p,
|
|
|
|
struct blkcipher_req_ctx *req_ctx,
|
|
|
|
struct scatterlist *dst,
|
|
|
|
struct scatterlist *src,
|
|
|
|
unsigned int ivsize,
|
|
|
|
void *areq,
|
|
|
|
void __iomem *cc_base)
|
2017-08-10 13:25:24 +00:00
|
|
|
{
|
|
|
|
int completion_error = 0;
|
2017-09-05 02:31:27 +00:00
|
|
|
u32 inflight_counter;
|
2017-09-10 12:49:22 +00:00
|
|
|
struct ablkcipher_request *req = (struct ablkcipher_request *)areq;
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
|
|
|
|
|
|
|
|
/*Set the inflight couter value to local variable*/
|
|
|
|
inflight_counter = ctx_p->drvdata->inflight_counter;
|
|
|
|
/*Decrease the inflight counter*/
|
2017-09-05 02:31:27 +00:00
|
|
|
if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
|
2017-08-10 13:25:24 +00:00
|
|
|
ctx_p->drvdata->inflight_counter--;
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
if (areq) {
|
2017-09-10 12:49:22 +00:00
|
|
|
/*
|
|
|
|
* The crypto API expects us to set the req->info to the last
|
|
|
|
* ciphertext block. For encrypt, simply copy from the result.
|
|
|
|
* For decrypt, we must copy from a saved buffer since this
|
|
|
|
* could be an in-place decryption operation and the src is
|
|
|
|
* lost by this point.
|
|
|
|
*/
|
|
|
|
if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
|
|
|
|
memcpy(req->info, req_ctx->backup_info, ivsize);
|
|
|
|
kfree(req_ctx->backup_info);
|
|
|
|
} else {
|
|
|
|
scatterwalk_map_and_copy(req->info, req->dst,
|
|
|
|
(req->nbytes - ivsize),
|
|
|
|
ivsize, 0);
|
|
|
|
}
|
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
ablkcipher_request_complete(areq, completion_error);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return completion_error;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ssi_blkcipher_process(
|
|
|
|
struct crypto_tfm *tfm,
|
|
|
|
struct blkcipher_req_ctx *req_ctx,
|
|
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
|
|
unsigned int nbytes,
|
|
|
|
void *info, //req info
|
|
|
|
unsigned int ivsize,
|
2017-09-05 02:31:27 +00:00
|
|
|
void *areq,
|
2017-08-10 13:25:24 +00:00
|
|
|
enum drv_crypto_direction direction)
|
|
|
|
{
|
|
|
|
struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
|
|
|
|
struct device *dev = &ctx_p->drvdata->plat_dev->dev;
|
2017-09-05 02:31:27 +00:00
|
|
|
struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN];
|
2017-08-10 13:25:24 +00:00
|
|
|
struct ssi_crypto_req ssi_req = {};
|
2017-09-05 02:31:27 +00:00
|
|
|
int rc, seq_len = 0, cts_restore_flag = 0;
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
SSI_LOG_DEBUG("%s areq=%p info=%p nbytes=%d\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"),
|
|
|
|
areq, info, nbytes);
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
/* STAT_PHASE_0: Init and sanity checks */
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
/* TODO: check data length according to mode */
|
|
|
|
if (unlikely(validate_data_size(ctx_p, nbytes))) {
|
|
|
|
SSI_LOG_ERR("Unsupported data size %d.\n", nbytes);
|
|
|
|
crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN);
|
2017-09-10 12:49:22 +00:00
|
|
|
rc = -EINVAL;
|
|
|
|
goto exit_process;
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
|
|
|
if (nbytes == 0) {
|
|
|
|
/* No data to process is valid */
|
2017-09-10 12:49:22 +00:00
|
|
|
rc = 0;
|
|
|
|
goto exit_process;
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
2017-09-05 02:31:27 +00:00
|
|
|
/*For CTS in case of data size aligned to 16 use CBC mode*/
|
|
|
|
if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)) {
|
2017-08-10 13:25:24 +00:00
|
|
|
ctx_p->cipher_mode = DRV_CIPHER_CBC;
|
|
|
|
cts_restore_flag = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup DX request structure */
|
|
|
|
ssi_req.user_cb = (void *)ssi_ablkcipher_complete;
|
|
|
|
ssi_req.user_arg = (void *)areq;
|
|
|
|
|
|
|
|
#ifdef ENABLE_CYCLE_COUNT
|
|
|
|
ssi_req.op_type = (direction == DRV_CRYPTO_DIRECTION_DECRYPT) ?
|
|
|
|
STAT_OP_TYPE_DECODE : STAT_OP_TYPE_ENCODE;
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Setup request context */
|
|
|
|
req_ctx->gen_ctx.op_type = direction;
|
|
|
|
|
|
|
|
/* STAT_PHASE_1: Map buffers */
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
rc = ssi_buffer_mgr_map_blkcipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes, info, src, dst);
|
|
|
|
if (unlikely(rc != 0)) {
|
|
|
|
SSI_LOG_ERR("map_request() failed\n");
|
|
|
|
goto exit_process;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* STAT_PHASE_2: Create sequence */
|
|
|
|
|
|
|
|
/* Setup processing */
|
|
|
|
#if SSI_CC_HAS_MULTI2
|
2017-09-05 02:31:27 +00:00
|
|
|
if (ctx_p->flow_mode == S_DIN_to_MULTI2)
|
|
|
|
ssi_blkcipher_create_multi2_setup_desc(tfm, req_ctx, ivsize,
|
|
|
|
desc, &seq_len);
|
|
|
|
else
|
2017-08-10 13:25:24 +00:00
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
2017-09-05 02:31:27 +00:00
|
|
|
ssi_blkcipher_create_setup_desc(tfm, req_ctx, ivsize, nbytes,
|
|
|
|
desc, &seq_len);
|
2017-08-10 13:25:24 +00:00
|
|
|
/* Data processing */
|
2017-10-03 17:33:45 +00:00
|
|
|
ssi_blkcipher_create_data_desc(tfm, req_ctx, dst, src, nbytes, areq,
|
|
|
|
desc, &seq_len);
|
2017-08-10 13:25:24 +00:00
|
|
|
|
|
|
|
/* do we need to generate IV? */
|
2017-09-05 02:31:27 +00:00
|
|
|
if (req_ctx->is_giv) {
|
2017-08-10 13:25:24 +00:00
|
|
|
ssi_req.ivgen_dma_addr[0] = req_ctx->gen_ctx.iv_dma_addr;
|
|
|
|
ssi_req.ivgen_dma_addr_len = 1;
|
|
|
|
/* set the IV size (8/16 B long)*/
|
|
|
|
ssi_req.ivgen_size = ivsize;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* STAT_PHASE_3: Lock HW and push sequence */
|
2017-09-05 02:31:27 +00:00
|
|
|
|
|
|
|
rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (!areq) ? 0 : 1);
|
|
|
|
if (areq) {
|
2017-08-10 13:25:24 +00:00
|
|
|
if (unlikely(rc != -EINPROGRESS)) {
|
|
|
|
/* Failed to send the request or request completed synchronously */
|
|
|
|
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
|
|
|
if (rc != 0) {
|
|
|
|
ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
|
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
rc = ssi_blkcipher_complete(dev, ctx_p, req_ctx, dst,
|
|
|
|
src, ivsize, NULL,
|
|
|
|
ctx_p->drvdata->cc_base);
|
|
|
|
}
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
exit_process:
|
|
|
|
if (cts_restore_flag != 0)
|
|
|
|
ctx_p->cipher_mode = DRV_CIPHER_CBC_CTS;
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-09-10 12:49:22 +00:00
|
|
|
if (rc != -EINPROGRESS)
|
|
|
|
kfree(req_ctx->backup_info);
|
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __iomem *cc_base)
|
|
|
|
{
|
|
|
|
struct ablkcipher_request *areq = (struct ablkcipher_request *)ssi_req;
|
|
|
|
struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(areq);
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
|
|
|
|
struct ssi_ablkcipher_ctx *ctx_p = crypto_ablkcipher_ctx(tfm);
|
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
ssi_blkcipher_complete(dev, ctx_p, req_ctx, areq->dst, areq->src,
|
|
|
|
ivsize, areq, cc_base);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Async wrap functions */
|
|
|
|
|
|
|
|
static int ssi_ablkcipher_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct ablkcipher_tfm *ablktfm = &tfm->crt_ablkcipher;
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
ablktfm->reqsize = sizeof(struct blkcipher_req_ctx);
|
|
|
|
|
|
|
|
return ssi_blkcipher_init(tfm);
|
|
|
|
}
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *tfm,
|
2017-10-03 17:33:45 +00:00
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
2017-08-10 13:25:24 +00:00
|
|
|
{
|
|
|
|
return ssi_blkcipher_setkey(crypto_ablkcipher_tfm(tfm), key, keylen);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ssi_ablkcipher_encrypt(struct ablkcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk_tfm);
|
|
|
|
struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req);
|
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm);
|
|
|
|
|
|
|
|
req_ctx->is_giv = false;
|
|
|
|
|
|
|
|
return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, req->nbytes, req->info, ivsize, (void *)req, DRV_CRYPTO_DIRECTION_ENCRYPT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablk_tfm);
|
|
|
|
struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req);
|
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(ablk_tfm);
|
|
|
|
|
2017-09-10 12:49:22 +00:00
|
|
|
/*
|
|
|
|
* Allocate and save the last IV sized bytes of the source, which will
|
|
|
|
* be lost in case of in-place decryption and might be needed for CTS.
|
|
|
|
*/
|
|
|
|
req_ctx->backup_info = kmalloc(ivsize, GFP_KERNEL);
|
|
|
|
if (!req_ctx->backup_info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
scatterwalk_map_and_copy(req_ctx->backup_info, req->src,
|
|
|
|
(req->nbytes - ivsize), ivsize, 0);
|
2017-08-10 13:25:24 +00:00
|
|
|
req_ctx->is_giv = false;
|
2017-09-10 12:49:22 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, req->nbytes, req->info, ivsize, (void *)req, DRV_CRYPTO_DIRECTION_DECRYPT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* DX Block cipher alg */
|
|
|
|
static struct ssi_alg_template blkcipher_algs[] = {
|
|
|
|
/* Async template */
|
|
|
|
#if SSI_CC_HAS_AES_XTS
|
|
|
|
{
|
|
|
|
.name = "xts(aes)",
|
|
|
|
.driver_name = "xts-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.geniv = "eseqiv",
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_XTS,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "xts(aes)",
|
|
|
|
.driver_name = "xts-aes-du512-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_XTS,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "xts(aes)",
|
|
|
|
.driver_name = "xts-aes-du4096-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_XTS,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
#endif /*SSI_CC_HAS_AES_XTS*/
|
|
|
|
#if SSI_CC_HAS_AES_ESSIV
|
|
|
|
{
|
|
|
|
.name = "essiv(aes)",
|
|
|
|
.driver_name = "essiv-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ESSIV,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "essiv(aes)",
|
|
|
|
.driver_name = "essiv-aes-du512-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ESSIV,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "essiv(aes)",
|
|
|
|
.driver_name = "essiv-aes-du4096-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ESSIV,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
#endif /*SSI_CC_HAS_AES_ESSIV*/
|
|
|
|
#if SSI_CC_HAS_AES_BITLOCKER
|
|
|
|
{
|
|
|
|
.name = "bitlocker(aes)",
|
|
|
|
.driver_name = "bitlocker-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_BITLOCKER,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "bitlocker(aes)",
|
|
|
|
.driver_name = "bitlocker-aes-du512-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_BITLOCKER,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "bitlocker(aes)",
|
|
|
|
.driver_name = "bitlocker-aes-du4096-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE * 2,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE * 2,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_BITLOCKER,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
#endif /*SSI_CC_HAS_AES_BITLOCKER*/
|
|
|
|
{
|
|
|
|
.name = "ecb(aes)",
|
|
|
|
.driver_name = "ecb-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = 0,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ECB,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "cbc(aes)",
|
|
|
|
.driver_name = "cbc-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
2017-09-05 02:31:27 +00:00
|
|
|
},
|
2017-08-10 13:25:24 +00:00
|
|
|
.cipher_mode = DRV_CIPHER_CBC,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ofb(aes)",
|
|
|
|
.driver_name = "ofb-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_OFB,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
#if SSI_CC_HAS_AES_CTS
|
|
|
|
{
|
|
|
|
.name = "cts1(cbc(aes))",
|
|
|
|
.driver_name = "cts1-cbc-aes-dx",
|
|
|
|
.blocksize = AES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_CBC_CTS,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
.name = "ctr(aes)",
|
|
|
|
.driver_name = "ctr-aes-dx",
|
|
|
|
.blocksize = 1,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_CTR,
|
|
|
|
.flow_mode = S_DIN_to_AES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "cbc(des3_ede)",
|
|
|
|
.driver_name = "cbc-3des-dx",
|
|
|
|
.blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.ivsize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_CBC,
|
|
|
|
.flow_mode = S_DIN_to_DES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ecb(des3_ede)",
|
|
|
|
.driver_name = "ecb-3des-dx",
|
|
|
|
.blocksize = DES3_EDE_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.max_keysize = DES3_EDE_KEY_SIZE,
|
|
|
|
.ivsize = 0,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ECB,
|
|
|
|
.flow_mode = S_DIN_to_DES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "cbc(des)",
|
|
|
|
.driver_name = "cbc-des-dx",
|
|
|
|
.blocksize = DES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
|
|
.max_keysize = DES_KEY_SIZE,
|
|
|
|
.ivsize = DES_BLOCK_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_CBC,
|
|
|
|
.flow_mode = S_DIN_to_DES,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ecb(des)",
|
|
|
|
.driver_name = "ecb-des-dx",
|
|
|
|
.blocksize = DES_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = DES_KEY_SIZE,
|
|
|
|
.max_keysize = DES_KEY_SIZE,
|
|
|
|
.ivsize = 0,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_CIPHER_ECB,
|
|
|
|
.flow_mode = S_DIN_to_DES,
|
|
|
|
},
|
|
|
|
#if SSI_CC_HAS_MULTI2
|
|
|
|
{
|
|
|
|
.name = "cbc(multi2)",
|
|
|
|
.driver_name = "cbc-multi2-dx",
|
|
|
|
.blocksize = CC_MULTI2_BLOCK_SIZE,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_decrypt,
|
|
|
|
.min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1,
|
|
|
|
.max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1,
|
|
|
|
.ivsize = CC_MULTI2_IV_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_MULTI2_CBC,
|
|
|
|
.flow_mode = S_DIN_to_MULTI2,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "ofb(multi2)",
|
|
|
|
.driver_name = "ofb-multi2-dx",
|
|
|
|
.blocksize = 1,
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
|
|
|
|
.template_ablkcipher = {
|
|
|
|
.setkey = ssi_ablkcipher_setkey,
|
|
|
|
.encrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.decrypt = ssi_ablkcipher_encrypt,
|
|
|
|
.min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1,
|
|
|
|
.max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1,
|
|
|
|
.ivsize = CC_MULTI2_IV_SIZE,
|
|
|
|
},
|
|
|
|
.cipher_mode = DRV_MULTI2_OFB,
|
|
|
|
.flow_mode = S_DIN_to_MULTI2,
|
|
|
|
},
|
|
|
|
#endif /*SSI_CC_HAS_MULTI2*/
|
|
|
|
};
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
static
|
2017-08-10 13:25:24 +00:00
|
|
|
struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *template)
|
|
|
|
{
|
|
|
|
struct ssi_crypto_alg *t_alg;
|
|
|
|
struct crypto_alg *alg;
|
|
|
|
|
2017-10-03 17:33:45 +00:00
|
|
|
t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (!t_alg) {
|
|
|
|
SSI_LOG_ERR("failed to allocate t_alg\n");
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
alg = &t_alg->crypto_alg;
|
|
|
|
|
|
|
|
snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
|
|
|
|
snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
|
|
|
|
template->driver_name);
|
|
|
|
alg->cra_module = THIS_MODULE;
|
|
|
|
alg->cra_priority = SSI_CRA_PRIO;
|
|
|
|
alg->cra_blocksize = template->blocksize;
|
|
|
|
alg->cra_alignmask = 0;
|
|
|
|
alg->cra_ctxsize = sizeof(struct ssi_ablkcipher_ctx);
|
2017-09-05 02:31:27 +00:00
|
|
|
|
|
|
|
alg->cra_init = ssi_ablkcipher_init;
|
|
|
|
alg->cra_exit = ssi_blkcipher_exit;
|
|
|
|
alg->cra_type = &crypto_ablkcipher_type;
|
|
|
|
alg->cra_ablkcipher = template->template_ablkcipher;
|
|
|
|
alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
|
2017-08-10 13:25:24 +00:00
|
|
|
template->type;
|
|
|
|
|
|
|
|
t_alg->cipher_mode = template->cipher_mode;
|
|
|
|
t_alg->flow_mode = template->flow_mode;
|
|
|
|
|
|
|
|
return t_alg;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ssi_ablkcipher_free(struct ssi_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
struct ssi_crypto_alg *t_alg, *n;
|
2017-09-05 02:31:27 +00:00
|
|
|
struct ssi_blkcipher_handle *blkcipher_handle =
|
2017-08-10 13:25:24 +00:00
|
|
|
drvdata->blkcipher_handle;
|
|
|
|
struct device *dev;
|
2017-09-05 02:31:27 +00:00
|
|
|
|
2017-08-10 13:25:24 +00:00
|
|
|
dev = &drvdata->plat_dev->dev;
|
|
|
|
|
2017-09-05 02:31:27 +00:00
|
|
|
if (blkcipher_handle) {
|
2017-08-10 13:25:24 +00:00
|
|
|
/* Remove registered algs */
|
|
|
|
list_for_each_entry_safe(t_alg, n,
|
2017-10-03 17:33:45 +00:00
|
|
|
&blkcipher_handle->blkcipher_alg_list,
|
2017-08-10 13:25:24 +00:00
|
|
|
entry) {
|
|
|
|
crypto_unregister_alg(&t_alg->crypto_alg);
|
|
|
|
list_del(&t_alg->entry);
|
|
|
|
kfree(t_alg);
|
|
|
|
}
|
|
|
|
kfree(blkcipher_handle);
|
|
|
|
drvdata->blkcipher_handle = NULL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata)
|
|
|
|
{
|
|
|
|
struct ssi_blkcipher_handle *ablkcipher_handle;
|
|
|
|
struct ssi_crypto_alg *t_alg;
|
|
|
|
int rc = -ENOMEM;
|
|
|
|
int alg;
|
|
|
|
|
2017-10-03 17:33:45 +00:00
|
|
|
ablkcipher_handle = kmalloc(sizeof(*ablkcipher_handle), GFP_KERNEL);
|
2017-09-05 02:31:27 +00:00
|
|
|
if (!ablkcipher_handle)
|
2017-08-10 13:25:24 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
drvdata->blkcipher_handle = ablkcipher_handle;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&ablkcipher_handle->blkcipher_alg_list);
|
|
|
|
|
|
|
|
/* Linux crypto */
|
|
|
|
SSI_LOG_DEBUG("Number of algorithms = %zu\n", ARRAY_SIZE(blkcipher_algs));
|
|
|
|
for (alg = 0; alg < ARRAY_SIZE(blkcipher_algs); alg++) {
|
|
|
|
SSI_LOG_DEBUG("creating %s\n", blkcipher_algs[alg].driver_name);
|
|
|
|
t_alg = ssi_ablkcipher_create_alg(&blkcipher_algs[alg]);
|
|
|
|
if (IS_ERR(t_alg)) {
|
|
|
|
rc = PTR_ERR(t_alg);
|
|
|
|
SSI_LOG_ERR("%s alg allocation failed\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
blkcipher_algs[alg].driver_name);
|
2017-08-10 13:25:24 +00:00
|
|
|
goto fail0;
|
|
|
|
}
|
|
|
|
t_alg->drvdata = drvdata;
|
|
|
|
|
|
|
|
SSI_LOG_DEBUG("registering %s\n", blkcipher_algs[alg].driver_name);
|
|
|
|
rc = crypto_register_alg(&t_alg->crypto_alg);
|
|
|
|
SSI_LOG_DEBUG("%s alg registration rc = %x\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
t_alg->crypto_alg.cra_driver_name, rc);
|
2017-08-10 13:25:24 +00:00
|
|
|
if (unlikely(rc != 0)) {
|
|
|
|
SSI_LOG_ERR("%s alg registration failed\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
t_alg->crypto_alg.cra_driver_name);
|
2017-08-10 13:25:24 +00:00
|
|
|
kfree(t_alg);
|
|
|
|
goto fail0;
|
|
|
|
} else {
|
2017-09-05 02:31:27 +00:00
|
|
|
list_add_tail(&t_alg->entry,
|
2017-08-10 13:25:24 +00:00
|
|
|
&ablkcipher_handle->blkcipher_alg_list);
|
2017-09-05 02:31:27 +00:00
|
|
|
SSI_LOG_DEBUG("Registered %s\n",
|
2017-10-03 17:33:45 +00:00
|
|
|
t_alg->crypto_alg.cra_driver_name);
|
2017-08-10 13:25:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail0:
|
|
|
|
ssi_ablkcipher_free(drvdata);
|
|
|
|
return rc;
|
|
|
|
}
|