82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
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/*
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* asm/metag_isa.h
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*
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* Copyright (C) 2000-2007, 2012 Imagination Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*
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* Various defines for Meta instruction set.
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*/
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#ifndef _ASM_METAG_ISA_H_
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#define _ASM_METAG_ISA_H_
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/* L1 cache layout */
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/* Data cache line size as bytes and shift */
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#define DCACHE_LINE_BYTES 64
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#define DCACHE_LINE_S 6
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/* Number of ways in the data cache */
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#define DCACHE_WAYS 4
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/* Instruction cache line size as bytes and shift */
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#define ICACHE_LINE_BYTES 64
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#define ICACHE_LINE_S 6
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/* Number of ways in the instruction cache */
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#define ICACHE_WAYS 4
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/*
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* CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to
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* control the operation actually achieved.
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*/
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/* Use of these two bits should be discouraged since the bits dont have
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* consistent meanings
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*/
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#define CACHEW_ICACHE_BIT 0x01
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#define CACHEW_TLBFLUSH_BIT 0x02
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#define CACHEW_FLUSH_L1D_L2 0x0
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#define CACHEW_INVALIDATE_L1I 0x1
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#define CACHEW_INVALIDATE_L1DTLB 0x2
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#define CACHEW_INVALIDATE_L1ITLB 0x3
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#define CACHEW_WRITEBACK_L1D_L2 0x4
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#define CACHEW_INVALIDATE_L1D 0x8
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#define CACHEW_INVALIDATE_L1D_L2 0xC
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/*
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* CACHERD/CACHERL instructions use bits 3:5 of the address presented to
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* control the operation achieved and hence the specific result.
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*/
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#define CACHER_ADDR_BITS 0xFFFFFFC0
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#define CACHER_OPER_BITS 0x00000030
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#define CACHER_OPER_S 4
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#define CACHER_OPER_LINPHY 0
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#define CACHER_ICACHE_BIT 0x00000008
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#define CACHER_ICACHE_S 3
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/*
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* CACHERD/CACHERL LINPHY Oper result is one/two 32-bit words
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*
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* If CRLINPHY0_VAL_BIT (Bit 0) set then,
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* Lower 32-bits corresponds to MMCU_ENTRY_* above.
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* Upper 32-bits corresponds to CRLINPHY1_* values below (if requested).
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* else
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* Lower 32-bits corresponds to CRLINPHY0_* values below.
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* Upper 32-bits undefined.
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*/
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#define CRLINPHY0_VAL_BIT 0x00000001
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#define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */
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#define CRLINPHY1_READ_BIT 0x00000001 /* Set if reads permitted */
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#define CRLINPHY1_SINGLE_BIT 0x00000004 /* Set if TLB does not cache entry */
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#define CRLINPHY1_PAGEMSK_BITS 0x0000FFF0 /* Set to ((2^n-1)>>12) value */
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#define CRLINPHY1_PAGEMSK_S 4
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#endif /* _ASM_METAG_ISA_H_ */
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