2021-08-14 23:44:09 +00:00
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From fc0e880581864996091eb1493106cfa688499e54 Mon Sep 17 00:00:00 2001
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2021-07-20 23:13:45 +00:00
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From: Sachi King <nakato@nakato.io>
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Date: Sat, 29 May 2021 22:27:25 +1000
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Subject: [PATCH] platform/x86: amd-pmc: Add device HID for AMD PMC
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The Surface Laptop 4 appears to have used AMD0005 for the PMC instead of
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the AMDI0005 which would match the ACPI ID Registry.
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AMD appears to have previously used "AMD" in a number of IDs in the past,
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and AMD is not allocated to any other entity as an ID, so adding this ID
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should not cause any harm.
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Signed-off-by: Sachi King <nakato@nakato.io>
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Patchset: amd-s0ix
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---
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drivers/platform/x86/amd-pmc.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
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2021-08-14 23:44:09 +00:00
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index ca95c2a52e26..65a81d295beb 100644
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2021-07-20 23:13:45 +00:00
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--- a/drivers/platform/x86/amd-pmc.c
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+++ b/drivers/platform/x86/amd-pmc.c
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2021-08-14 23:44:09 +00:00
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@@ -299,6 +299,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
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2021-07-20 23:13:45 +00:00
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static const struct acpi_device_id amd_pmc_acpi_ids[] = {
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{"AMDI0005", 0},
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{"AMD0004", 0},
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+ {"AMD0005", 0},
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
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--
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2.32.0
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2021-08-14 23:44:09 +00:00
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From b7decf4829b6fc0eee95391b7586ef4f358d0665 Mon Sep 17 00:00:00 2001
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2021-07-20 23:13:45 +00:00
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From: Marcin Bachry <hegel666@gmail.com>
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Date: Tue, 16 Mar 2021 15:28:51 -0400
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Subject: [PATCH] PCI: quirks: Quirk PCI d3hot delay for AMD xhci
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Renoir needs a similar delay.
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Signed-off-by: Marcin Bachry <hegel666@gmail.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Patchset: amd-s0ix
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---
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drivers/pci/quirks.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
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index 6d74386eadc2..446f8f7b0ee4 100644
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -1900,6 +1900,9 @@ static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
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+/* Renoir XHCI requires longer delay when transitioning from D0 to
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+ * D3hot */
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+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
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#ifdef CONFIG_X86_IO_APIC
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static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
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--
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2.32.0
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2021-08-14 23:44:09 +00:00
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From 9aa59beca56f76169a52013ee2373fe544d90ec5 Mon Sep 17 00:00:00 2001
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2021-07-20 23:13:45 +00:00
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Wed, 9 Jun 2021 13:40:17 -0500
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Subject: [PATCH] ACPI: Check StorageD3Enable _DSD property in ACPI code
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Although first implemented for NVME, this check may be usable by
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other drivers as well. Microsoft's specification explicitly mentions
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that is may be usable by SATA and AHCI devices. Google also indicates
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that they have used this with SDHCI in a downstream kernel tree that
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a user can plug a storage device into.
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Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro
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Suggested-by: Keith Busch <kbusch@kernel.org>
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CC: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com>
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CC: Alexander Deucher <Alexander.Deucher@amd.com>
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CC: Rafael J. Wysocki <rjw@rjwysocki.net>
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CC: Prike Liang <prike.liang@amd.com>
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Signed-off-by: Christoph Hellwig <hch@lst.de>
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Patchset: amd-s0ix
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---
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drivers/acpi/device_pm.c | 29 +++++++++++++++++++++++++++++
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drivers/nvme/host/pci.c | 28 +---------------------------
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include/linux/acpi.h | 5 +++++
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3 files changed, 35 insertions(+), 27 deletions(-)
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diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
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index 9d2d3b9bb8b5..b20ae93415f0 100644
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--- a/drivers/acpi/device_pm.c
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+++ b/drivers/acpi/device_pm.c
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@@ -1338,4 +1338,33 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on)
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return 1;
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}
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EXPORT_SYMBOL_GPL(acpi_dev_pm_attach);
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+
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+/**
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+ * acpi_storage_d3 - Check if D3 should be used in the suspend path
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+ * @dev: Device to check
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+ *
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+ * Return %true if the platform firmware wants @dev to be programmed
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+ * into D3hot or D3cold (if supported) in the suspend path, or %false
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+ * when there is no specific preference. On some platforms, if this
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+ * hint is ignored, @dev may remain unresponsive after suspending the
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+ * platform as a whole.
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+ *
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+ * Although the property has storage in the name it actually is
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+ * applied to the PCIe slot and plugging in a non-storage device the
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+ * same platform restrictions will likely apply.
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+ */
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+bool acpi_storage_d3(struct device *dev)
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+{
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+ struct acpi_device *adev = ACPI_COMPANION(dev);
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+ u8 val;
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+
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+ if (!adev)
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+ return false;
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+ if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
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+ &val))
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+ return false;
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+ return val == 1;
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+}
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+EXPORT_SYMBOL_GPL(acpi_storage_d3);
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+
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#endif /* CONFIG_PM */
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diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
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2021-08-01 14:01:49 +00:00
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index d963f25fc7ae..66455e2261d0 100644
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2021-07-20 23:13:45 +00:00
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--- a/drivers/nvme/host/pci.c
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+++ b/drivers/nvme/host/pci.c
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2021-08-01 14:01:49 +00:00
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@@ -2880,32 +2880,6 @@ static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
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2021-07-20 23:13:45 +00:00
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return 0;
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}
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-#ifdef CONFIG_ACPI
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-static bool nvme_acpi_storage_d3(struct pci_dev *dev)
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-{
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- struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
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- u8 val;
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-
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- /*
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- * Look for _DSD property specifying that the storage device on the port
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- * must use D3 to support deep platform power savings during
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- * suspend-to-idle.
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- */
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-
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- if (!adev)
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- return false;
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- if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
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- &val))
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- return false;
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- return val == 1;
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-}
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-#else
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-static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
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-{
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- return false;
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-}
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-#endif /* CONFIG_ACPI */
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-
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static void nvme_async_probe(void *data, async_cookie_t cookie)
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{
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struct nvme_dev *dev = data;
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2021-08-01 14:01:49 +00:00
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@@ -2955,7 +2929,7 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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2021-07-20 23:13:45 +00:00
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quirks |= check_vendor_combination_bug(pdev);
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- if (!noacpi && nvme_acpi_storage_d3(pdev)) {
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+ if (!noacpi && acpi_storage_d3(&pdev->dev)) {
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/*
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* Some systems use a bios work around to ask for D3 on
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* platforms that support kernel managed suspend.
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diff --git a/include/linux/acpi.h b/include/linux/acpi.h
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index e8ba7063c000..66c43abef4a4 100644
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--- a/include/linux/acpi.h
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+++ b/include/linux/acpi.h
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@@ -1006,6 +1006,7 @@ int acpi_dev_resume(struct device *dev);
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int acpi_subsys_runtime_suspend(struct device *dev);
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int acpi_subsys_runtime_resume(struct device *dev);
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int acpi_dev_pm_attach(struct device *dev, bool power_on);
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+bool acpi_storage_d3(struct device *dev);
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#else
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static inline int acpi_subsys_runtime_suspend(struct device *dev) { return 0; }
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static inline int acpi_subsys_runtime_resume(struct device *dev) { return 0; }
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@@ -1013,6 +1014,10 @@ static inline int acpi_dev_pm_attach(struct device *dev, bool power_on)
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{
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return 0;
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}
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+static inline bool acpi_storage_d3(struct device *dev)
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+{
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+ return false;
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+}
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#endif
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#if defined(CONFIG_ACPI) && defined(CONFIG_PM_SLEEP)
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--
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2.32.0
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2021-08-14 23:44:09 +00:00
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From 42069e4fbfb7443575d45864ce21fd97810dc354 Mon Sep 17 00:00:00 2001
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2021-07-20 23:13:45 +00:00
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Wed, 9 Jun 2021 13:40:18 -0500
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Subject: [PATCH] ACPI: Add quirks for AMD Renoir/Lucienne CPUs to force the D3
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hint
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AMD systems from Renoir and Lucienne require that the NVME controller
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is put into D3 over a Modern Standby / suspend-to-idle
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cycle. This is "typically" accomplished using the `StorageD3Enable`
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property in the _DSD, but this property was introduced after many
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of these systems launched and most OEM systems don't have it in
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their BIOS.
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On AMD Renoir without these drives going into D3 over suspend-to-idle
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the resume will fail with the NVME controller being reset and a trace
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like this in the kernel logs:
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```
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[ 83.556118] nvme nvme0: I/O 161 QID 2 timeout, aborting
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[ 83.556178] nvme nvme0: I/O 162 QID 2 timeout, aborting
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[ 83.556187] nvme nvme0: I/O 163 QID 2 timeout, aborting
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[ 83.556196] nvme nvme0: I/O 164 QID 2 timeout, aborting
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[ 95.332114] nvme nvme0: I/O 25 QID 0 timeout, reset controller
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[ 95.332843] nvme nvme0: Abort status: 0x371
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[ 95.332852] nvme nvme0: Abort status: 0x371
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[ 95.332856] nvme nvme0: Abort status: 0x371
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[ 95.332859] nvme nvme0: Abort status: 0x371
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[ 95.332909] PM: dpm_run_callback(): pci_pm_resume+0x0/0xe0 returns -16
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[ 95.332936] nvme 0000:03:00.0: PM: failed to resume async: error -16
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```
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The Microsoft documentation for StorageD3Enable mentioned that Windows has
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a hardcoded allowlist for D3 support, which was used for these platforms.
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Introduce quirks to hardcode them for Linux as well.
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As this property is now "standardized", OEM systems using AMD Cezanne and
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newer APU's have adopted this property, and quirks like this should not be
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necessary.
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CC: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com>
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CC: Alexander Deucher <Alexander.Deucher@amd.com>
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CC: Prike Liang <prike.liang@amd.com>
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Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Tested-by: Julian Sikorski <belegdol@gmail.com>
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Signed-off-by: Christoph Hellwig <hch@lst.de>
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Patchset: amd-s0ix
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---
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drivers/acpi/device_pm.c | 3 +++
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drivers/acpi/internal.h | 9 +++++++++
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drivers/acpi/x86/utils.c | 25 +++++++++++++++++++++++++
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3 files changed, 37 insertions(+)
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diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
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index b20ae93415f0..0cfdef2fc3ad 100644
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--- a/drivers/acpi/device_pm.c
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+++ b/drivers/acpi/device_pm.c
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@@ -1358,6 +1358,9 @@ bool acpi_storage_d3(struct device *dev)
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struct acpi_device *adev = ACPI_COMPANION(dev);
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u8 val;
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+ if (force_storage_d3())
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+ return true;
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+
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if (!adev)
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return false;
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if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
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diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
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index e21611c9a170..7ac01b03ba67 100644
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--- a/drivers/acpi/internal.h
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+++ b/drivers/acpi/internal.h
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@@ -236,6 +236,15 @@ static inline int suspend_nvs_save(void) { return 0; }
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static inline void suspend_nvs_restore(void) {}
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#endif
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+#ifdef CONFIG_X86
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+bool force_storage_d3(void);
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+#else
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+static inline bool force_storage_d3(void)
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+{
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+ return false;
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+}
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+#endif
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+
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/*--------------------------------------------------------------------------
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Device properties
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-------------------------------------------------------------------------- */
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diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c
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index bdc1ba00aee9..5298bb4d81fe 100644
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--- a/drivers/acpi/x86/utils.c
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+++ b/drivers/acpi/x86/utils.c
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@@ -135,3 +135,28 @@ bool acpi_device_always_present(struct acpi_device *adev)
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return ret;
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}
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+
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+/*
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+ * AMD systems from Renoir and Lucienne *require* that the NVME controller
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|
|
+ * is put into D3 over a Modern Standby / suspend-to-idle cycle.
|
|
|
|
+ *
|
|
|
|
+ * This is "typically" accomplished using the `StorageD3Enable`
|
|
|
|
+ * property in the _DSD that is checked via the `acpi_storage_d3` function
|
|
|
|
+ * but this property was introduced after many of these systems launched
|
|
|
|
+ * and most OEM systems don't have it in their BIOS.
|
|
|
|
+ *
|
|
|
|
+ * The Microsoft documentation for StorageD3Enable mentioned that Windows has
|
|
|
|
+ * a hardcoded allowlist for D3 support, which was used for these platforms.
|
|
|
|
+ *
|
|
|
|
+ * This allows quirking on Linux in a similar fashion.
|
|
|
|
+ */
|
|
|
|
+const struct x86_cpu_id storage_d3_cpu_ids[] = {
|
|
|
|
+ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /* Renoir */
|
|
|
|
+ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL), /* Lucienne */
|
|
|
|
+ {}
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+bool force_storage_d3(void)
|
|
|
|
+{
|
|
|
|
+ return x86_match_cpu(storage_d3_cpu_ids);
|
|
|
|
+}
|
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From 7e06f35deb6284d96879a6a58b84a421aff69b8f Mon Sep 17 00:00:00 2001
|
2021-07-20 23:13:45 +00:00
|
|
|
From: Alex Deucher <alexander.deucher@amd.com>
|
|
|
|
Date: Wed, 17 Mar 2021 10:38:42 -0400
|
|
|
|
Subject: [PATCH] platform/x86: force LPS0 functions for AMD
|
|
|
|
|
|
|
|
ACPI_LPS0_ENTRY_AMD/ACPI_LPS0_EXIT_AMD are supposedly not
|
|
|
|
required for AMD platforms, and on some platforms they are
|
|
|
|
not even listed in the function mask but at least some HP
|
|
|
|
laptops seem to require it to properly support s0ix.
|
|
|
|
|
|
|
|
Based on a patch from Marcin Bachry <hegel666@gmail.com>.
|
|
|
|
|
|
|
|
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1230
|
|
|
|
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
|
|
Cc: Marcin Bachry <hegel666@gmail.com>
|
|
|
|
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
|
|
|
|
Patchset: amd-s0ix
|
|
|
|
---
|
|
|
|
drivers/acpi/x86/s2idle.c | 7 +++++++
|
|
|
|
1 file changed, 7 insertions(+)
|
|
|
|
|
|
|
|
diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
|
|
|
|
index 2d7ddb8a8cb6..482e6b23b21a 100644
|
|
|
|
--- a/drivers/acpi/x86/s2idle.c
|
|
|
|
+++ b/drivers/acpi/x86/s2idle.c
|
|
|
|
@@ -368,6 +368,13 @@ static int lps0_device_attach(struct acpi_device *adev,
|
|
|
|
|
|
|
|
ACPI_FREE(out_obj);
|
|
|
|
|
|
|
|
+ /*
|
|
|
|
+ * Some HP laptops require ACPI_LPS0_ENTRY_AMD/ACPI_LPS0_EXIT_AMD for proper
|
|
|
|
+ * S0ix, but don't set the function mask correctly. Fix that up here.
|
|
|
|
+ */
|
|
|
|
+ if (acpi_s2idle_vendor_amd())
|
|
|
|
+ lps0_dsm_func_mask |= (1 << ACPI_LPS0_ENTRY_AMD) | (1 << ACPI_LPS0_EXIT_AMD);
|
|
|
|
+
|
|
|
|
acpi_handle_debug(adev->handle, "_DSM function mask: 0x%x\n",
|
|
|
|
lps0_dsm_func_mask);
|
|
|
|
|
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From bd205b477ba24671f8e09be2c467de750b7c73ab Mon Sep 17 00:00:00 2001
|
|
|
|
From: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
|
|
|
|
Date: Thu, 17 Jun 2021 11:42:08 -0500
|
|
|
|
Subject: [PATCH] ACPI: PM: s2idle: Use correct revision id
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
AMD spec mentions only revision 0. With this change,
|
|
|
|
device constraint list is populated properly.
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
|
2021-07-20 23:13:45 +00:00
|
|
|
Patchset: amd-s0ix
|
|
|
|
---
|
2021-08-14 23:44:09 +00:00
|
|
|
drivers/acpi/x86/s2idle.c | 2 +-
|
|
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
|
|
|
|
index 482e6b23b21a..4339e6da0dd6 100644
|
|
|
|
--- a/drivers/acpi/x86/s2idle.c
|
|
|
|
+++ b/drivers/acpi/x86/s2idle.c
|
|
|
|
@@ -96,7 +96,7 @@ static void lpi_device_get_constraints_amd(void)
|
|
|
|
int i, j, k;
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
out_obj = acpi_evaluate_dsm_typed(lps0_device_handle, &lps0_dsm_guid,
|
|
|
|
- 1, ACPI_LPS0_GET_DEVICE_CONSTRAINTS,
|
|
|
|
+ rev_id, ACPI_LPS0_GET_DEVICE_CONSTRAINTS,
|
|
|
|
NULL, ACPI_TYPE_PACKAGE);
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
if (!out_obj)
|
2021-07-20 23:13:45 +00:00
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From d02cfd1749187cd8dc7997a9268a5d6629a2f31a Mon Sep 17 00:00:00 2001
|
2021-07-20 23:13:45 +00:00
|
|
|
From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Date: Tue, 29 Jun 2021 14:17:59 +0530
|
|
|
|
Subject: [PATCH] platform/x86: amd-pmc: call dump registers only once
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
Currently amd_pmc_dump_registers() routine is being called at
|
|
|
|
multiple places. The best to call it is after command submission
|
|
|
|
to SMU.
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
|
2021-07-20 23:13:45 +00:00
|
|
|
Patchset: amd-s0ix
|
|
|
|
---
|
2021-08-14 23:44:09 +00:00
|
|
|
drivers/platform/x86/amd-pmc.c | 5 +----
|
|
|
|
1 file changed, 1 insertion(+), 4 deletions(-)
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
|
2021-08-14 23:44:09 +00:00
|
|
|
index 65a81d295beb..d08ff5907e4c 100644
|
2021-07-20 23:13:45 +00:00
|
|
|
--- a/drivers/platform/x86/amd-pmc.c
|
|
|
|
+++ b/drivers/platform/x86/amd-pmc.c
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -182,6 +182,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
|
2021-07-20 23:13:45 +00:00
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
out_unlock:
|
|
|
|
mutex_unlock(&dev->lock);
|
2021-07-20 23:13:45 +00:00
|
|
|
+ amd_pmc_dump_registers(dev);
|
2021-08-14 23:44:09 +00:00
|
|
|
return rc;
|
2021-07-20 23:13:45 +00:00
|
|
|
}
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -194,7 +195,6 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
if (rc)
|
|
|
|
dev_err(pdev->dev, "suspend failed\n");
|
|
|
|
|
|
|
|
- amd_pmc_dump_registers(pdev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -207,7 +207,6 @@ static int __maybe_unused amd_pmc_resume(struct device *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
if (rc)
|
|
|
|
dev_err(pdev->dev, "resume failed\n");
|
|
|
|
|
|
|
|
- amd_pmc_dump_registers(pdev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -279,8 +278,6 @@ static int amd_pmc_probe(struct platform_device *pdev)
|
2021-07-20 23:13:45 +00:00
|
|
|
if (!dev->regbase)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
- amd_pmc_dump_registers(dev);
|
|
|
|
-
|
2021-08-14 23:44:09 +00:00
|
|
|
mutex_init(&dev->lock);
|
2021-07-20 23:13:45 +00:00
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
amd_pmc_dbgfs_register(dev);
|
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From 9367cb28c141d148d626c81d6109b08abb6caa31 Mon Sep 17 00:00:00 2001
|
2021-07-20 23:13:45 +00:00
|
|
|
From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Date: Tue, 29 Jun 2021 14:18:00 +0530
|
2021-07-20 23:13:45 +00:00
|
|
|
Subject: [PATCH] platform/x86: amd-pmc: Add support for logging SMU metrics
|
|
|
|
|
|
|
|
SMU provides a way to dump the s0ix debug statistics in the form of a
|
|
|
|
metrics table via a of set special mailbox commands.
|
|
|
|
|
|
|
|
Add support to the driver which can send these commands to SMU and expose
|
|
|
|
the information received via debugfs. The information contains the s0ix
|
|
|
|
entry/exit, active time of each IP block etc.
|
|
|
|
|
|
|
|
As a side note, SMU subsystem logging is not supported on Picasso based
|
|
|
|
SoC's.
|
|
|
|
|
|
|
|
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
|
2021-07-20 23:13:45 +00:00
|
|
|
Patchset: amd-s0ix
|
|
|
|
---
|
2021-08-14 23:44:09 +00:00
|
|
|
drivers/platform/x86/amd-pmc.c | 147 +++++++++++++++++++++++++++++++--
|
|
|
|
1 file changed, 139 insertions(+), 8 deletions(-)
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
|
2021-08-14 23:44:09 +00:00
|
|
|
index d08ff5907e4c..cfa5c44bb170 100644
|
2021-07-20 23:13:45 +00:00
|
|
|
--- a/drivers/platform/x86/amd-pmc.c
|
|
|
|
+++ b/drivers/platform/x86/amd-pmc.c
|
|
|
|
@@ -46,6 +46,14 @@
|
|
|
|
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
|
|
|
|
#define AMD_PMC_RESULT_FAILED 0xFF
|
|
|
|
|
|
|
|
+/* SMU Message Definations */
|
|
|
|
+#define SMU_MSG_GETSMUVERSION 0x02
|
|
|
|
+#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
|
|
|
|
+#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
|
|
|
|
+#define SMU_MSG_LOG_START 0x06
|
|
|
|
+#define SMU_MSG_LOG_RESET 0x07
|
|
|
|
+#define SMU_MSG_LOG_DUMP_DATA 0x08
|
|
|
|
+#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
|
|
|
|
/* List of supported CPU ids */
|
|
|
|
#define AMD_CPU_ID_RV 0x15D0
|
|
|
|
#define AMD_CPU_ID_RN 0x1630
|
|
|
|
@@ -55,17 +63,42 @@
|
|
|
|
#define PMC_MSG_DELAY_MIN_US 100
|
|
|
|
#define RESPONSE_REGISTER_LOOP_MAX 200
|
|
|
|
|
|
|
|
+#define SOC_SUBSYSTEM_IP_MAX 12
|
|
|
|
+#define DELAY_MIN_US 2000
|
|
|
|
+#define DELAY_MAX_US 3000
|
|
|
|
enum amd_pmc_def {
|
|
|
|
MSG_TEST = 0x01,
|
|
|
|
MSG_OS_HINT_PCO,
|
|
|
|
MSG_OS_HINT_RN,
|
|
|
|
};
|
|
|
|
|
|
|
|
+struct amd_pmc_bit_map {
|
|
|
|
+ const char *name;
|
|
|
|
+ u32 bit_mask;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static const struct amd_pmc_bit_map soc15_ip_blk[] = {
|
|
|
|
+ {"DISPLAY", BIT(0)},
|
|
|
|
+ {"CPU", BIT(1)},
|
|
|
|
+ {"GFX", BIT(2)},
|
|
|
|
+ {"VDD", BIT(3)},
|
|
|
|
+ {"ACP", BIT(4)},
|
|
|
|
+ {"VCN", BIT(5)},
|
|
|
|
+ {"ISP", BIT(6)},
|
|
|
|
+ {"NBIO", BIT(7)},
|
|
|
|
+ {"DF", BIT(8)},
|
|
|
|
+ {"USB0", BIT(9)},
|
|
|
|
+ {"USB1", BIT(10)},
|
|
|
|
+ {"LAPIC", BIT(11)},
|
|
|
|
+ {}
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
struct amd_pmc_dev {
|
|
|
|
void __iomem *regbase;
|
|
|
|
- void __iomem *smu_base;
|
|
|
|
+ void __iomem *smu_virt_addr;
|
|
|
|
u32 base_addr;
|
|
|
|
u32 cpu_id;
|
|
|
|
+ u32 active_ips;
|
|
|
|
struct device *dev;
|
2021-08-14 23:44:09 +00:00
|
|
|
struct mutex lock; /* generic mutex lock */
|
2021-07-20 23:13:45 +00:00
|
|
|
#if IS_ENABLED(CONFIG_DEBUG_FS)
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -74,6 +107,7 @@ struct amd_pmc_dev {
|
2021-07-20 23:13:45 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct amd_pmc_dev pmc;
|
|
|
|
+static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret);
|
|
|
|
|
|
|
|
static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
|
|
|
|
{
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -85,9 +119,49 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
|
2021-07-20 23:13:45 +00:00
|
|
|
iowrite32(val, dev->regbase + reg_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
+struct smu_metrics {
|
|
|
|
+ u32 table_version;
|
|
|
|
+ u32 hint_count;
|
|
|
|
+ u32 s0i3_cyclecount;
|
|
|
|
+ u32 timein_s0i2;
|
|
|
|
+ u64 timeentering_s0i3_lastcapture;
|
|
|
|
+ u64 timeentering_s0i3_totaltime;
|
|
|
|
+ u64 timeto_resume_to_os_lastcapture;
|
|
|
|
+ u64 timeto_resume_to_os_totaltime;
|
|
|
|
+ u64 timein_s0i3_lastcapture;
|
|
|
|
+ u64 timein_s0i3_totaltime;
|
|
|
|
+ u64 timein_swdrips_lastcapture;
|
|
|
|
+ u64 timein_swdrips_totaltime;
|
|
|
|
+ u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
|
|
|
|
+ u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
|
|
|
|
+} __packed;
|
|
|
|
+
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
static int smu_fw_info_show(struct seq_file *s, void *unused)
|
|
|
|
{
|
|
|
|
+ struct amd_pmc_dev *dev = s->private;
|
|
|
|
+ struct smu_metrics table;
|
|
|
|
+ int idx;
|
|
|
|
+
|
|
|
|
+ if (dev->cpu_id == AMD_CPU_ID_PCO)
|
|
|
|
+ return -EINVAL;
|
|
|
|
+
|
|
|
|
+ memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
|
|
|
|
+
|
|
|
|
+ seq_puts(s, "\n=== SMU Statistics ===\n");
|
|
|
|
+ seq_printf(s, "Table Version: %d\n", table.table_version);
|
|
|
|
+ seq_printf(s, "Hint Count: %d\n", table.hint_count);
|
|
|
|
+ seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);
|
|
|
|
+ seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
|
|
|
|
+ seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
|
|
|
|
+
|
|
|
|
+ seq_puts(s, "\n=== Active time (in us) ===\n");
|
|
|
|
+ for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
|
|
|
|
+ if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
|
|
|
|
+ seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
|
|
|
|
+ table.timecondition_notmet_lastcapture[idx]);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -113,6 +187,32 @@ static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
}
|
|
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
|
|
|
|
+static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
|
|
|
|
+{
|
|
|
|
+ u32 phys_addr_low, phys_addr_hi;
|
|
|
|
+ u64 smu_phys_addr;
|
|
|
|
+
|
|
|
|
+ if (dev->cpu_id == AMD_CPU_ID_PCO)
|
|
|
|
+ return -EINVAL;
|
|
|
|
+
|
|
|
|
+ /* Get Active devices list from SMU */
|
|
|
|
+ amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
|
|
|
|
+
|
|
|
|
+ /* Get dram address */
|
|
|
|
+ amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
|
|
|
|
+ amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
|
|
|
|
+ smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
|
|
|
|
+
|
|
|
|
+ dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
|
|
|
|
+ if (!dev->smu_virt_addr)
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
+ /* Start the logging */
|
|
|
|
+ amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
|
|
|
|
{
|
|
|
|
u32 value;
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -127,10 +227,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
|
|
|
|
}
|
|
|
|
|
|
|
|
-static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
|
|
|
|
+static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
- u8 msg;
|
|
|
|
u32 val;
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
mutex_lock(&dev->lock);
|
|
|
|
@@ -150,8 +249,8 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
|
2021-07-20 23:13:45 +00:00
|
|
|
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
|
|
|
|
|
|
|
|
/* Write message ID to message ID register */
|
|
|
|
- msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
|
|
|
|
amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
|
|
|
|
+
|
|
|
|
/* Wait until we get a valid response */
|
|
|
|
rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
|
2021-08-14 23:44:09 +00:00
|
|
|
val, val != 0, PMC_MSG_DELAY_MIN_US,
|
|
|
|
@@ -163,6 +262,11 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
|
|
|
|
|
|
|
|
switch (val) {
|
|
|
|
case AMD_PMC_RESULT_OK:
|
|
|
|
+ if (ret) {
|
|
|
|
+ /* PMFW may take longer time to return back the data */
|
|
|
|
+ usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
|
|
|
|
+ *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
|
|
|
|
+ }
|
|
|
|
break;
|
|
|
|
case AMD_PMC_RESULT_CMD_REJECT_BUSY:
|
|
|
|
dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
|
|
|
|
@@ -186,12 +290,29 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
|
|
|
|
return rc;
|
2021-07-20 23:13:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
+static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
|
|
|
|
+{
|
|
|
|
+ switch (dev->cpu_id) {
|
|
|
|
+ case AMD_CPU_ID_PCO:
|
|
|
|
+ return MSG_OS_HINT_PCO;
|
|
|
|
+ case AMD_CPU_ID_RN:
|
|
|
|
+ return MSG_OS_HINT_RN;
|
|
|
|
+ }
|
|
|
|
+ return -EINVAL;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
static int __maybe_unused amd_pmc_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
|
|
|
|
int rc;
|
|
|
|
+ u8 msg;
|
2021-08-14 23:44:09 +00:00
|
|
|
|
|
|
|
- rc = amd_pmc_send_cmd(pdev, 1);
|
2021-07-20 23:13:45 +00:00
|
|
|
+ /* Reset and Start SMU logging - to monitor the s0i3 stats */
|
|
|
|
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
|
|
|
|
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
|
2021-08-14 23:44:09 +00:00
|
|
|
+
|
2021-07-20 23:13:45 +00:00
|
|
|
+ msg = amd_pmc_get_os_hint(pdev);
|
|
|
|
+ rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);
|
|
|
|
if (rc)
|
|
|
|
dev_err(pdev->dev, "suspend failed\n");
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -202,8 +323,13 @@ static int __maybe_unused amd_pmc_resume(struct device *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
{
|
|
|
|
struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
|
|
|
|
int rc;
|
|
|
|
+ u8 msg;
|
|
|
|
|
|
|
|
- rc = amd_pmc_send_cmd(pdev, 0);
|
2021-08-14 23:44:09 +00:00
|
|
|
+ /* Let SMU know that we are looking for stats */
|
|
|
|
+ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
|
|
|
|
+
|
2021-07-20 23:13:45 +00:00
|
|
|
+ msg = amd_pmc_get_os_hint(pdev);
|
|
|
|
+ rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
|
|
|
|
if (rc)
|
|
|
|
dev_err(pdev->dev, "resume failed\n");
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -226,8 +352,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
|
2021-07-20 23:13:45 +00:00
|
|
|
{
|
|
|
|
struct amd_pmc_dev *dev = &pmc;
|
|
|
|
struct pci_dev *rdev;
|
|
|
|
- u32 base_addr_lo;
|
|
|
|
- u32 base_addr_hi;
|
|
|
|
+ u32 base_addr_lo, base_addr_hi;
|
|
|
|
u64 base_addr;
|
|
|
|
int err;
|
|
|
|
u32 val;
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -279,6 +404,12 @@ static int amd_pmc_probe(struct platform_device *pdev)
|
2021-07-20 23:13:45 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
mutex_init(&dev->lock);
|
|
|
|
+
|
2021-07-20 23:13:45 +00:00
|
|
|
+ /* Use SMU to get the s0i3 debug stats */
|
|
|
|
+ err = amd_pmc_setup_smu_logging(dev);
|
|
|
|
+ if (err)
|
|
|
|
+ dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
|
2021-08-14 23:44:09 +00:00
|
|
|
+
|
2021-07-20 23:13:45 +00:00
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
amd_pmc_dbgfs_register(dev);
|
|
|
|
return 0;
|
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From 392e1a4e917612d31b844402838a5579ac69a53c Mon Sep 17 00:00:00 2001
|
2021-07-20 23:13:45 +00:00
|
|
|
From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Date: Tue, 29 Jun 2021 14:18:01 +0530
|
|
|
|
Subject: [PATCH] amd-pmc: Add support for logging s0ix counters
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
Even the FCH SSC registers provides certain level of information
|
|
|
|
about the s0ix entry and exit times which comes handy when the SMU
|
|
|
|
fails to report the statistics via the mailbox communication.
|
|
|
|
|
|
|
|
This information is captured via a new debugfs file "s0ix_stats".
|
|
|
|
A non-zero entry in this counters would mean that the system entered
|
|
|
|
the s0ix state.
|
|
|
|
|
|
|
|
If s0ix entry time and exit time don't change during suspend to idle,
|
|
|
|
the silicon has not entered the deepest state.
|
|
|
|
|
|
|
|
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
|
2021-07-20 23:13:45 +00:00
|
|
|
Patchset: amd-s0ix
|
|
|
|
---
|
2021-08-14 23:44:09 +00:00
|
|
|
drivers/platform/x86/amd-pmc.c | 45 +++++++++++++++++++++++++++++++++-
|
|
|
|
1 file changed, 44 insertions(+), 1 deletion(-)
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
|
2021-08-14 23:44:09 +00:00
|
|
|
index cfa5c44bb170..d1db12e28b32 100644
|
2021-07-20 23:13:45 +00:00
|
|
|
--- a/drivers/platform/x86/amd-pmc.c
|
|
|
|
+++ b/drivers/platform/x86/amd-pmc.c
|
|
|
|
@@ -46,6 +46,15 @@
|
|
|
|
#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
|
|
|
|
#define AMD_PMC_RESULT_FAILED 0xFF
|
|
|
|
|
|
|
|
+/* FCH SSC Registers */
|
|
|
|
+#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
|
|
|
|
+#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
|
|
|
|
+#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
|
|
|
|
+#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
|
|
|
|
+#define FCH_SSC_MAPPING_SIZE 0x800
|
|
|
|
+#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
|
|
|
|
+#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
|
|
|
|
+
|
|
|
|
/* SMU Message Definations */
|
|
|
|
#define SMU_MSG_GETSMUVERSION 0x02
|
|
|
|
#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
|
|
|
|
@@ -96,6 +105,7 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = {
|
|
|
|
struct amd_pmc_dev {
|
|
|
|
void __iomem *regbase;
|
|
|
|
void __iomem *smu_virt_addr;
|
|
|
|
+ void __iomem *fch_virt_addr;
|
|
|
|
u32 base_addr;
|
|
|
|
u32 cpu_id;
|
|
|
|
u32 active_ips;
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -166,6 +176,29 @@ static int smu_fw_info_show(struct seq_file *s, void *unused)
|
2021-07-20 23:13:45 +00:00
|
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
|
|
|
|
|
|
|
|
+static int s0ix_stats_show(struct seq_file *s, void *unused)
|
|
|
|
+{
|
|
|
|
+ struct amd_pmc_dev *dev = s->private;
|
|
|
|
+ u64 entry_time, exit_time, residency;
|
|
|
|
+
|
|
|
|
+ entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
|
|
|
|
+ entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
|
|
|
|
+
|
|
|
|
+ exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
|
|
|
|
+ exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
|
|
|
|
+
|
2021-08-14 23:44:09 +00:00
|
|
|
+ /* It's in 48MHz. We need to convert it */
|
|
|
|
+ residency = (exit_time - entry_time) / 48;
|
2021-07-20 23:13:45 +00:00
|
|
|
+
|
|
|
|
+ seq_puts(s, "=== S0ix statistics ===\n");
|
|
|
|
+ seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
|
|
|
|
+ seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
|
|
|
|
+ seq_printf(s, "Residency Time: %lld\n", residency);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
|
|
|
|
+
|
|
|
|
static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
|
|
|
|
{
|
|
|
|
debugfs_remove_recursive(dev->dbgfs_dir);
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -176,6 +209,8 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
|
2021-07-20 23:13:45 +00:00
|
|
|
dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
|
|
|
|
debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
|
|
|
|
&smu_fw_info_fops);
|
|
|
|
+ debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
|
|
|
|
+ &s0ix_stats_fops);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -353,7 +388,7 @@ static int amd_pmc_probe(struct platform_device *pdev)
|
2021-07-20 23:13:45 +00:00
|
|
|
struct amd_pmc_dev *dev = &pmc;
|
|
|
|
struct pci_dev *rdev;
|
|
|
|
u32 base_addr_lo, base_addr_hi;
|
|
|
|
- u64 base_addr;
|
|
|
|
+ u64 base_addr, fch_phys_addr;
|
|
|
|
int err;
|
|
|
|
u32 val;
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
@@ -405,6 +440,14 @@ static int amd_pmc_probe(struct platform_device *pdev)
|
|
|
|
|
|
|
|
mutex_init(&dev->lock);
|
2021-07-20 23:13:45 +00:00
|
|
|
|
|
|
|
+ /* Use FCH registers to get the S0ix stats */
|
|
|
|
+ base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
|
|
|
|
+ base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
|
|
|
|
+ fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
|
|
|
|
+ dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
|
|
|
|
+ if (!dev->fch_virt_addr)
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
/* Use SMU to get the s0i3 debug stats */
|
|
|
|
err = amd_pmc_setup_smu_logging(dev);
|
|
|
|
if (err)
|
|
|
|
--
|
|
|
|
2.32.0
|
|
|
|
|
2021-08-14 23:44:09 +00:00
|
|
|
From d49720e8fb987ec9acd4c761e6840f3e4e6708cc Mon Sep 17 00:00:00 2001
|
2021-07-20 23:13:45 +00:00
|
|
|
From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
|
2021-08-14 23:44:09 +00:00
|
|
|
Date: Tue, 29 Jun 2021 14:18:02 +0530
|
2021-07-20 23:13:45 +00:00
|
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Subject: [PATCH] platform/x86: amd-pmc: Add support for ACPI ID AMDI0006
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Some newer BIOSes have added another ACPI ID for the uPEP device.
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SMU statistics behave identically on this device.
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Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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2021-08-14 23:44:09 +00:00
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Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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2021-07-20 23:13:45 +00:00
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Patchset: amd-s0ix
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---
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drivers/platform/x86/amd-pmc.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
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2021-08-14 23:44:09 +00:00
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index d1db12e28b32..b8740daecd7b 100644
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2021-07-20 23:13:45 +00:00
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--- a/drivers/platform/x86/amd-pmc.c
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+++ b/drivers/platform/x86/amd-pmc.c
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2021-08-14 23:44:09 +00:00
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@@ -469,6 +469,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
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2021-07-20 23:13:45 +00:00
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static const struct acpi_device_id amd_pmc_acpi_ids[] = {
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{"AMDI0005", 0},
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+ {"AMDI0006", 0},
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{"AMD0004", 0},
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{"AMD0005", 0},
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{ }
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--
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2.32.0
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2021-08-14 23:44:09 +00:00
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From 99a19092cfd53f582701d10b32ec98747581be23 Mon Sep 17 00:00:00 2001
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2021-07-20 23:13:45 +00:00
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From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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2021-08-14 23:44:09 +00:00
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Date: Tue, 29 Jun 2021 14:18:03 +0530
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2021-07-20 23:13:45 +00:00
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Subject: [PATCH] platform/x86: amd-pmc: Add new acpi id for future PMC
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controllers
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The upcoming PMC controller would have a newer acpi id, add that to
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the supported acpid device list.
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Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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2021-08-14 23:44:09 +00:00
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Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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2021-07-20 23:13:45 +00:00
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Patchset: amd-s0ix
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---
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drivers/platform/x86/amd-pmc.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
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2021-08-14 23:44:09 +00:00
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index b8740daecd7b..267173b142c1 100644
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2021-07-20 23:13:45 +00:00
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--- a/drivers/platform/x86/amd-pmc.c
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+++ b/drivers/platform/x86/amd-pmc.c
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@@ -68,6 +68,7 @@
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#define AMD_CPU_ID_RN 0x1630
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#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
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#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
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+#define AMD_CPU_ID_YC 0x14B5
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#define PMC_MSG_DELAY_MIN_US 100
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#define RESPONSE_REGISTER_LOOP_MAX 200
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2021-08-14 23:44:09 +00:00
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@@ -331,6 +332,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
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2021-07-20 23:13:45 +00:00
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case AMD_CPU_ID_PCO:
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return MSG_OS_HINT_PCO;
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case AMD_CPU_ID_RN:
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+ case AMD_CPU_ID_YC:
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return MSG_OS_HINT_RN;
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}
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return -EINVAL;
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2021-08-14 23:44:09 +00:00
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@@ -376,6 +378,7 @@ static const struct dev_pm_ops amd_pmc_pm_ops = {
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2021-07-20 23:13:45 +00:00
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};
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static const struct pci_device_id pmc_pci_ids[] = {
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+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
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2021-08-14 23:44:09 +00:00
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@@ -470,6 +473,7 @@ static int amd_pmc_remove(struct platform_device *pdev)
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2021-07-20 23:13:45 +00:00
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static const struct acpi_device_id amd_pmc_acpi_ids[] = {
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{"AMDI0005", 0},
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{"AMDI0006", 0},
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+ {"AMDI0007", 0},
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{"AMD0004", 0},
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{"AMD0005", 0},
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{ }
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--
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2.32.0
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