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https://github.com/LadybirdBrowser/ladybird.git
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e5500e2a22
The alternate status register is not part of the same set of registers as all the other stuff. Also rename wait_400ns() to io_delay() since we had no guarantee that it was waiting for 400ns..
530 lines
15 KiB
C++
530 lines
15 KiB
C++
#include "PATADiskDevice.h"
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#include <AK/ByteBuffer.h>
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#include <Kernel/Devices/PATAChannel.h>
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#include <Kernel/FileSystem/ProcFS.h>
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#include <Kernel/IO.h>
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#include <Kernel/Process.h>
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#include <Kernel/VM/MemoryManager.h>
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#define PATA_PRIMARY_IRQ 14
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#define PATA_SECONDARY_IRQ 15
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//#define PATA_DEBUG
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#define ATA_SR_BSY 0x80
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#define ATA_SR_DRDY 0x40
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#define ATA_SR_DF 0x20
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#define ATA_SR_DSC 0x10
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#define ATA_SR_DRQ 0x08
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#define ATA_SR_CORR 0x04
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#define ATA_SR_IDX 0x02
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#define ATA_SR_ERR 0x01
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#define ATA_ER_BBK 0x80
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#define ATA_ER_UNC 0x40
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#define ATA_ER_MC 0x20
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#define ATA_ER_IDNF 0x10
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#define ATA_ER_MCR 0x08
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#define ATA_ER_ABRT 0x04
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#define ATA_ER_TK0NF 0x02
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#define ATA_ER_AMNF 0x01
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#define ATA_CMD_READ_PIO 0x20
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#define ATA_CMD_READ_PIO_EXT 0x24
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#define ATA_CMD_READ_DMA 0xC8
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_PIO 0x30
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#define ATA_CMD_WRITE_PIO_EXT 0x34
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#define ATA_CMD_WRITE_DMA 0xCA
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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#define ATA_CMD_CACHE_FLUSH 0xE7
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#define ATA_CMD_CACHE_FLUSH_EXT 0xEA
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#define ATA_CMD_PACKET 0xA0
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATAPI_CMD_READ 0xA8
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#define ATAPI_CMD_EJECT 0x1B
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#define ATA_IDENT_DEVICETYPE 0
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#define ATA_IDENT_CYLINDERS 2
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#define ATA_IDENT_HEADS 6
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#define ATA_IDENT_SECTORS 12
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#define ATA_IDENT_SERIAL 20
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#define ATA_IDENT_MODEL 54
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#define ATA_IDENT_CAPABILITIES 98
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#define ATA_IDENT_FIELDVALID 106
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#define ATA_IDENT_MAX_LBA 120
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#define ATA_IDENT_COMMANDSETS 164
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#define ATA_IDENT_MAX_LBA_EXT 200
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#define IDE_ATA 0x00
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#define IDE_ATAPI 0x01
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#define ATA_REG_DATA 0x00
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#define ATA_REG_ERROR 0x01
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#define ATA_REG_FEATURES 0x01
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#define ATA_REG_SECCOUNT0 0x02
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#define ATA_REG_LBA0 0x03
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#define ATA_REG_LBA1 0x04
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#define ATA_REG_LBA2 0x05
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#define ATA_REG_HDDEVSEL 0x06
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#define ATA_REG_COMMAND 0x07
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#define ATA_REG_STATUS 0x07
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#define ATA_CTL_CONTROL 0x00
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#define ATA_CTL_ALTSTATUS 0x00
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#define ATA_CTL_DEVADDRESS 0x01
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static Lock& s_lock()
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{
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static Lock* lock;
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if (!lock)
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lock = new Lock;
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return *lock;
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};
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OwnPtr<PATAChannel> PATAChannel::create(ChannelType type)
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{
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return make<PATAChannel>(type);
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}
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PATAChannel::PATAChannel(ChannelType type)
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: IRQHandler((type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ))
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, m_channel_number((type == ChannelType::Primary ? 0 : 1))
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, m_io_base((type == ChannelType::Primary ? 0x1F0 : 0x170))
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, m_control_base((type == ChannelType::Primary ? 0x3f6 : 0x376))
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{
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m_dma_enabled.resource() = true;
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ProcFS::add_sys_bool("ide_dma", m_dma_enabled);
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initialize();
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detect_disks();
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}
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PATAChannel::~PATAChannel()
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{
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}
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void PATAChannel::initialize()
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{
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static const PCI::ID piix3_ide_id = { 0x8086, 0x7010 };
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static const PCI::ID piix4_ide_id = { 0x8086, 0x7111 };
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PCI::enumerate_all([this](const PCI::Address& address, PCI::ID id) {
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if (id == piix3_ide_id || id == piix4_ide_id) {
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m_pci_address = address;
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kprintf("PATAChannel: PIIX%u PATA Controller found!\n", id == piix3_ide_id ? 3 : 4);
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}
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});
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// Let's try to set up DMA transfers.
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if (!m_pci_address.is_null()) {
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m_prdt.end_of_table = 0x8000;
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PCI::enable_bus_mastering(m_pci_address);
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m_bus_master_base = PCI::get_BAR4(m_pci_address) & 0xfffc;
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m_dma_buffer_page = MM.allocate_supervisor_physical_page();
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kprintf("PATAChannel: PIIX Bus master IDE: I/O @ %x\n", m_bus_master_base);
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}
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}
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static void print_ide_status(u8 status)
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{
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kprintf("PATAChannel: print_ide_status: DRQ=%u BSY=%u DRDY=%u DSC=%u DF=%u CORR=%u IDX=%u ERR=%u\n",
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(status & ATA_SR_DRQ) != 0,
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(status & ATA_SR_BSY) != 0,
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(status & ATA_SR_DRDY) != 0,
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(status & ATA_SR_DSC) != 0,
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(status & ATA_SR_DF) != 0,
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(status & ATA_SR_CORR) != 0,
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(status & ATA_SR_IDX) != 0,
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(status & ATA_SR_ERR) != 0);
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}
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bool PATAChannel::wait_for_irq()
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{
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#ifdef PATA_DEBUG
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kprintf("PATAChannel: waiting for IRQ %d...\n", irq_number());
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#endif
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while (!m_interrupted) {
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// FIXME: Put this process into a Blocked state instead, it's stupid to wake up just to check a flag.
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Scheduler::yield();
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}
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#ifdef PATA_DEBUG
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kprintf("PATAChannel: received IRQ %d!\n", irq_number());
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#endif
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return true;
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}
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void PATAChannel::handle_irq()
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{
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u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (status & ATA_SR_ERR) {
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print_ide_status(status);
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m_device_error = IO::in8(m_io_base + ATA_REG_ERROR);
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kprintf("PATAChannel: Error %b!\n", m_device_error);
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} else {
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m_device_error = 0;
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}
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#ifdef PATA_DEBUG
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kprintf("PATAChannel: interrupt: DRQ=%u BSY=%u DRDY=%u\n", (status & ATA_SR_DRQ) != 0, (status & ATA_SR_BSY) != 0, (status & ATA_SR_DRDY) != 0);
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#endif
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m_interrupted = true;
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}
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static void io_delay()
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{
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for (int i = 0; i < 4; ++i)
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IO::in8(0x3f6);
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}
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void PATAChannel::detect_disks()
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{
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// There are only two possible disks connected to a channel
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for (auto i = 0; i < 2; i++) {
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enable_irq();
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, 0xA0 | (i << 4)); // First, we need to select the drive itself
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// Apparently these need to be 0 before sending IDENTIFY?!
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, 0x00);
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IO::out8(m_io_base + ATA_REG_LBA0, 0x00);
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IO::out8(m_io_base + ATA_REG_LBA1, 0x00);
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IO::out8(m_io_base + ATA_REG_LBA2, 0x00);
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_IDENTIFY); // Send the ATA_IDENTIFY command
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// Wait for the BSY flag to be reset
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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if (IO::in8(m_io_base + ATA_REG_STATUS) == 0x00) {
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#ifdef PATA_DEBUG
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kprintf("PATAChannel: No %s disk detected!\n", (i == 0 ? "master" : "slave"));
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#endif
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continue;
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}
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ByteBuffer wbuf = ByteBuffer::create_uninitialized(512);
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ByteBuffer bbuf = ByteBuffer::create_uninitialized(512);
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u8* b = bbuf.pointer();
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u16* w = (u16*)wbuf.pointer();
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const u16* wbufbase = (u16*)wbuf.pointer();
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for (u32 i = 0; i < 256; ++i) {
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u16 data = IO::in16(m_io_base + ATA_REG_DATA);
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*(w++) = data;
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*(b++) = MSB(data);
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*(b++) = LSB(data);
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}
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// "Unpad" the device name string.
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for (u32 i = 93; i > 54 && bbuf[i] == ' '; --i)
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bbuf[i] = 0;
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u8 cyls = wbufbase[1];
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u8 heads = wbufbase[3];
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u8 spt = wbufbase[6];
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kprintf(
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"PATAChannel: Name=\"%s\", C/H/Spt=%u/%u/%u\n",
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bbuf.pointer() + 54,
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cyls,
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heads,
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spt);
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int major = (m_channel_number == 0) ? 3 : 4;
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if (i == 0) {
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m_master = PATADiskDevice::create(*this, PATADiskDevice::DriveType::Master, major, 0);
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m_master->set_drive_geometry(cyls, heads, spt);
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} else {
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m_slave = PATADiskDevice::create(*this, PATADiskDevice::DriveType::Slave, major, 1);
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m_slave->set_drive_geometry(cyls, heads, spt);
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}
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}
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}
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bool PATAChannel::ata_read_sectors_with_dma(u32 lba, u16 count, u8* outbuf, bool slave_request)
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{
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LOCKER(s_lock());
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#ifdef PATA_DEBUG
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kprintf("%s(%u): PATAChannel::ata_read_sectors_with_dma (%u x%u) -> %p\n",
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current->process().name().characters(),
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current->pid(), lba, count, outbuf);
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#endif
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disable_irq();
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m_prdt.offset = m_dma_buffer_page->paddr();
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m_prdt.size = 512 * count;
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ASSERT(m_prdt.size <= PAGE_SIZE);
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// Stop bus master
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IO::out8(m_bus_master_base, 0);
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// Write the PRDT location
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IO::out32(m_bus_master_base + 4, (u32)&m_prdt);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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// Set transfer direction
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IO::out8(m_bus_master_base, 0x8);
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m_interrupted = false;
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enable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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u8 devsel = 0xe0;
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if (slave_request)
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devsel |= 0x10;
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IO::out8(m_control_base + ATA_CTL_CONTROL, 0);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | (static_cast<u8>(slave_request) << 4));
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io_delay();
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IO::out8(m_io_base + ATA_REG_FEATURES, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, 0);
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IO::out8(m_io_base + ATA_REG_LBA0, 0);
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IO::out8(m_io_base + ATA_REG_LBA1, 0);
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IO::out8(m_io_base + ATA_REG_LBA2, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count);
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IO::out8(m_io_base + ATA_REG_LBA0, (lba & 0x000000ff) >> 0);
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IO::out8(m_io_base + ATA_REG_LBA1, (lba & 0x0000ff00) >> 8);
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IO::out8(m_io_base + ATA_REG_LBA2, (lba & 0x00ff0000) >> 16);
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for (;;) {
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auto status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_READ_DMA_EXT);
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io_delay();
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// Start bus master
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IO::out8(m_bus_master_base, 0x9);
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wait_for_irq();
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disable_irq();
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if (m_device_error)
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return false;
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memcpy(outbuf, m_dma_buffer_page->paddr().as_ptr(), 512 * count);
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// I read somewhere that this may trigger a cache flush so let's do it.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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return true;
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}
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bool PATAChannel::ata_write_sectors_with_dma(u32 lba, u16 count, const u8* inbuf, bool slave_request)
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{
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LOCKER(s_lock());
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#ifdef PATA_DEBUG
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kprintf("%s(%u): PATAChannel::ata_write_sectors_with_dma (%u x%u) <- %p\n",
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current->process().name().characters(),
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current->pid(), lba, count, inbuf);
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#endif
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disable_irq();
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m_prdt.offset = m_dma_buffer_page->paddr();
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m_prdt.size = 512 * count;
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memcpy(m_dma_buffer_page->paddr().as_ptr(), inbuf, 512 * count);
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ASSERT(m_prdt.size <= PAGE_SIZE);
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// Stop bus master
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IO::out8(m_bus_master_base, 0);
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// Write the PRDT location
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IO::out32(m_bus_master_base + 4, (u32)&m_prdt);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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m_interrupted = false;
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enable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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u8 devsel = 0xe0;
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if (slave_request)
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devsel |= 0x10;
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IO::out8(m_control_base + ATA_CTL_CONTROL, 0);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | (static_cast<u8>(slave_request) << 4));
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io_delay();
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IO::out8(m_io_base + ATA_REG_FEATURES, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, 0);
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IO::out8(m_io_base + ATA_REG_LBA0, 0);
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IO::out8(m_io_base + ATA_REG_LBA1, 0);
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IO::out8(m_io_base + ATA_REG_LBA2, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count);
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IO::out8(m_io_base + ATA_REG_LBA0, (lba & 0x000000ff) >> 0);
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IO::out8(m_io_base + ATA_REG_LBA1, (lba & 0x0000ff00) >> 8);
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IO::out8(m_io_base + ATA_REG_LBA2, (lba & 0x00ff0000) >> 16);
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for (;;) {
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auto status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_WRITE_DMA_EXT);
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io_delay();
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// Start bus master
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IO::out8(m_bus_master_base, 0x1);
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wait_for_irq();
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disable_irq();
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if (m_device_error)
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return false;
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// I read somewhere that this may trigger a cache flush so let's do it.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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return true;
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}
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bool PATAChannel::ata_read_sectors(u32 start_sector, u16 count, u8* outbuf, bool slave_request)
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{
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ASSERT(count <= 256);
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LOCKER(s_lock());
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#ifdef PATA_DEBUG
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kprintf("%s(%u): PATAChannel::ata_read_sectors request (%u sector(s) @ %u into %p)\n",
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current->process().name().characters(),
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current->pid(),
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count,
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start_sector,
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outbuf);
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#endif
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disable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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#ifdef PATA_DEBUG
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kprintf("PATAChannel: Reading %u sector(s) @ LBA %u\n", count, start_sector);
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#endif
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u8 devsel = 0xe0;
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if (slave_request)
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devsel |= 0x10;
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count == 256 ? 0 : LSB(count));
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IO::out8(m_io_base + ATA_REG_LBA0, start_sector & 0xff);
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IO::out8(m_io_base + ATA_REG_LBA1, (start_sector >> 8) & 0xff);
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IO::out8(m_io_base + ATA_REG_LBA2, (start_sector >> 16) & 0xff);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | ((start_sector >> 24) & 0xf));
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IO::out8(0x3F6, 0x08);
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while (!(IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_DRDY))
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;
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_READ_PIO);
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m_interrupted = false;
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enable_irq();
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wait_for_irq();
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if (m_device_error)
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return false;
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for (int i = 0; i < count; i++) {
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io_delay();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
|
|
;
|
|
|
|
u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
|
|
ASSERT(status & ATA_SR_DRQ);
|
|
#ifdef PATA_DEBUG
|
|
kprintf("PATAChannel: Retrieving 512 bytes (part %d) (status=%b), outbuf=%p...\n", i, status, outbuf + (512 * i));
|
|
#endif
|
|
|
|
IO::repeated_in16(m_io_base + ATA_REG_DATA, outbuf + (512 * i), 256);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool PATAChannel::ata_write_sectors(u32 start_sector, u16 count, const u8* inbuf, bool slave_request)
|
|
{
|
|
ASSERT(count <= 256);
|
|
LOCKER(s_lock());
|
|
#ifdef PATA_DEBUG
|
|
kprintf("%s(%u): PATAChannel::ata_write_sectors request (%u sector(s) @ %u)\n",
|
|
current->process().name().characters(),
|
|
current->pid(),
|
|
count,
|
|
start_sector);
|
|
#endif
|
|
disable_irq();
|
|
|
|
while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
|
|
;
|
|
|
|
#ifdef PATA_DEBUG
|
|
kprintf("PATAChannel: Writing %u sector(s) @ LBA %u\n", count, start_sector);
|
|
#endif
|
|
|
|
u8 devsel = 0xe0;
|
|
if (slave_request)
|
|
devsel |= 0x10;
|
|
|
|
IO::out8(m_io_base + ATA_REG_SECCOUNT0, count == 256 ? 0 : LSB(count));
|
|
IO::out8(m_io_base + ATA_REG_LBA0, start_sector & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_LBA1, (start_sector >> 8) & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_LBA2, (start_sector >> 16) & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | ((start_sector >> 24) & 0xf));
|
|
|
|
IO::out8(0x3F6, 0x08);
|
|
while (!(IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_DRDY))
|
|
;
|
|
|
|
IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_WRITE_PIO);
|
|
|
|
for (int i = 0; i < count; i++) {
|
|
io_delay();
|
|
while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
|
|
;
|
|
|
|
u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
|
|
ASSERT(status & ATA_SR_DRQ);
|
|
|
|
#ifdef PATA_DEBUG
|
|
kprintf("PATAChannel: Writing 512 bytes (part %d) (status=%b), inbuf=%p...\n", i, status, inbuf + (512 * i));
|
|
#endif
|
|
|
|
disable_irq();
|
|
IO::repeated_out16(m_io_base + ATA_REG_DATA, inbuf + (512 * i), 256);
|
|
m_interrupted = false;
|
|
enable_irq();
|
|
wait_for_irq();
|
|
status = IO::in8(m_io_base + ATA_REG_STATUS);
|
|
ASSERT(!(status & ATA_SR_BSY));
|
|
}
|
|
|
|
disable_irq();
|
|
IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_CACHE_FLUSH);
|
|
m_interrupted = false;
|
|
enable_irq();
|
|
wait_for_irq();
|
|
u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
|
|
ASSERT(!(status & ATA_SR_BSY));
|
|
|
|
return !m_device_error;
|
|
}
|