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6d2c298b66
As there is no need for a Prekernel on aarch64, the Prekernel code was moved into Kernel itself. The functionality remains the same. SERENITY_KERNEL_AND_INITRD in run.sh specifies a kernel and an inital ramdisk to be used by the emulator. This is needed because aarch64 does not need a Prekernel and the other ones do.
102 lines
3.5 KiB
C++
102 lines
3.5 KiB
C++
/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/aarch64/ASM_wrapper.h>
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#include <Kernel/Arch/aarch64/Aarch64_asm_utils.h>
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#include <Kernel/Arch/aarch64/Prekernel.h>
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#include <Kernel/Arch/aarch64/Registers.h>
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extern "C" void enter_el2_from_el3();
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extern "C" void enter_el1_from_el2();
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using namespace Kernel;
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namespace Prekernel {
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static void drop_to_el2()
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{
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Aarch64::SCR_EL3 secure_configuration_register_el3 = {};
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secure_configuration_register_el3.ST = 1; // Don't trap access to Counter-timer Physical Secure registers
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secure_configuration_register_el3.RW = 1; // Lower level to use Aarch64
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secure_configuration_register_el3.NS = 1; // Non-secure state
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secure_configuration_register_el3.HCE = 1; // Enable Hypervisor instructions at all levels
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Aarch64::SCR_EL3::write(secure_configuration_register_el3);
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Aarch64::SPSR_EL3 saved_program_status_register_el3 = {};
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// Mask (disable) all interrupts
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saved_program_status_register_el3.A = 1;
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saved_program_status_register_el3.I = 1;
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saved_program_status_register_el3.F = 1;
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saved_program_status_register_el3.D = 1;
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el3.M = Aarch64::SPSR_EL3::Mode::EL2t;
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// Set the register
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Aarch64::SPSR_EL3::write(saved_program_status_register_el3);
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// This will jump into os_start() below
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enter_el2_from_el3();
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}
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static void drop_to_el1()
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{
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Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {};
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hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
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Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
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Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
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// Mask (disable) all interrupts
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saved_program_status_register_el2.A = 1;
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saved_program_status_register_el2.I = 1;
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saved_program_status_register_el2.F = 1;
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el2.M = Aarch64::SPSR_EL2::Mode::EL1t;
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Aarch64::SPSR_EL2::write(saved_program_status_register_el2);
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enter_el1_from_el2();
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}
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static void set_up_el1()
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{
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Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value();
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system_control_register_el1.UCT = 1; // Don't trap access to CTR_EL0
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system_control_register_el1.nTWE = 1; // Don't trap WFE instructions
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system_control_register_el1.nTWI = 1; // Don't trap WFI instructions
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system_control_register_el1.DZE = 1; // Don't trap DC ZVA instructions
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system_control_register_el1.UMA = 1; // Don't trap access to DAIF (debugging) flags of EFLAGS register
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system_control_register_el1.SA0 = 1; // Enable stack access alignment check for EL0
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system_control_register_el1.SA = 1; // Enable stack access alignment check for EL1
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system_control_register_el1.A = 1; // Enable memory access alignment check
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Aarch64::SCTLR_EL1::write(system_control_register_el1);
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}
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void drop_to_exception_level_1()
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{
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switch (Kernel::Aarch64::Asm::get_current_exception_level()) {
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case Kernel::Aarch64::Asm::ExceptionLevel::EL3:
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drop_to_el2();
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[[fallthrough]];
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case Kernel::Aarch64::Asm::ExceptionLevel::EL2:
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drop_to_el1();
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[[fallthrough]];
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case Kernel::Aarch64::Asm::ExceptionLevel::EL1:
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set_up_el1();
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break;
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default: {
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Prekernel::panic("FATAL: CPU booted in unsupported exception mode!\r\n");
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}
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}
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}
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}
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