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Kernel: Support all Intel-defined extended CPUID feature flags for EAX=7
We're now able to detect all the extended CPUID feature flags from EBX/ECX/EDX for EAX=7 :^)
This commit is contained in:
Linus Groh
Andreas Kling
parent
6ca03b915e
commit
96e6420d8d
Notes:
sideshowbarker
2024-07-17 16:39:27 +09:00
Author: https://github.com/linusg Commit: https://github.com/SerenityOS/serenity/commit/96e6420d8d Pull-request: https://github.com/SerenityOS/serenity/pull/13290 Reviewed-by: https://github.com/bgianfo ✅
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@ -37,7 +37,7 @@ private:
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u32 m_edx { 0xffffffff };
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};
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
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/* EAX=1, ECX */ //
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SSE3 = CPUFeature(1u) << 0u, // Streaming SIMD Extensions 3
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PCLMULQDQ = CPUFeature(1u) << 1u, // PCLMULDQ Instruction
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@ -105,20 +105,105 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
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IA64 = CPUFeature(1u) << 62u, // IA64 processor emulating x86
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PBE = CPUFeature(1u) << 63u, // Pending Break Enable
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/* EAX=7, EBX */ //
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SMEP = CPUFeature(1u) << 64u, // Supervisor Mode Execution Protection
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RDSEED = CPUFeature(1u) << 65u, // RDSEED Instruction
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SMAP = CPUFeature(1u) << 66u, // Supervisor Mode Access Prevention
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FSGSBASE = CPUFeature(1u) << 64u, // Access to base of %fs and %gs
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TSC_ADJUST = CPUFeature(1u) << 65u, // IA32_TSC_ADJUST MSR
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SGX = CPUFeature(1u) << 66u, // Software Guard Extensions
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BMI1 = CPUFeature(1u) << 67u, // Bit Manipulation Instruction Set 1
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HLE = CPUFeature(1u) << 68u, // TSX Hardware Lock Elision
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AVX2 = CPUFeature(1u) << 69u, // Advanced Vector Extensions 2
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FDP_EXCPTN_ONLY = CPUFeature(1u) << 70u, // FDP_EXCPTN_ONLY
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SMEP = CPUFeature(1u) << 71u, // Supervisor Mode Execution Protection
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BMI2 = CPUFeature(1u) << 72u, // Bit Manipulation Instruction Set 2
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ERMS = CPUFeature(1u) << 73u, // Enhanced REP MOVSB/STOSB
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INVPCID = CPUFeature(1u) << 74u, // INVPCID Instruction
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RTM = CPUFeature(1u) << 75u, // TSX Restricted Transactional Memory
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PQM = CPUFeature(1u) << 76u, // Platform Quality of Service Monitoring
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ZERO_FCS_FDS = CPUFeature(1u) << 77u, // FPU CS and FPU DS deprecated
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MPX = CPUFeature(1u) << 78u, // Intel MPX (Memory Protection Extensions)
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PQE = CPUFeature(1u) << 79u, // Platform Quality of Service Enforcement
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AVX512_F = CPUFeature(1u) << 80u, // AVX-512 Foundation
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AVX512_DQ = CPUFeature(1u) << 81u, // AVX-512 Doubleword and Quadword Instructions
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RDSEED = CPUFeature(1u) << 82u, // RDSEED Instruction
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ADX = CPUFeature(1u) << 83u, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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SMAP = CPUFeature(1u) << 84u, // Supervisor Mode Access Prevention
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AVX512_IFMA = CPUFeature(1u) << 85u, // AVX-512 Integer Fused Multiply-Add Instructions
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PCOMMIT = CPUFeature(1u) << 86u, // PCOMMIT Instruction
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CLFLUSHOPT = CPUFeature(1u) << 87u, // CLFLUSHOPT Instruction
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CLWB = CPUFeature(1u) << 88u, // CLWB Instruction
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INTEL_PT = CPUFeature(1u) << 89u, // Intel Processor Tracing
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AVX512_PF = CPUFeature(1u) << 90u, // AVX-512 Prefetch Instructions
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AVX512_ER = CPUFeature(1u) << 91u, // AVX-512 Exponential and Reciprocal Instructions
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AVX512_CD = CPUFeature(1u) << 92u, // AVX-512 Conflict Detection Instructions
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SHA = CPUFeature(1u) << 93u, // Intel SHA Extensions
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AVX512_BW = CPUFeature(1u) << 94u, // AVX-512 Byte and Word Instructions
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AVX512_VL = CPUFeature(1u) << 95u, // AVX-512 Vector Length Extensions
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/* EAX=7, ECX */ //
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UMIP = CPUFeature(1u) << 67u, // User-Mode Instruction Prevention
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PREFETCHWT1 = CPUFeature(1u) << 96u, // PREFETCHWT1 Instruction
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AVX512_VBMI = CPUFeature(1u) << 97u, // AVX-512 Vector Bit Manipulation Instructions
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UMIP = CPUFeature(1u) << 98u, // UMIP
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PKU = CPUFeature(1u) << 99u, // Memory Protection Keys for User-mode pages
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OSPKU = CPUFeature(1u) << 100u, // PKU enabled by OS
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WAITPKG = CPUFeature(1u) << 101u, // Timed pause and user-level monitor/wait
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AVX512_VBMI2 = CPUFeature(1u) << 102u, // AVX-512 Vector Bit Manipulation Instructions 2
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CET_SS = CPUFeature(1u) << 103u, // Control Flow Enforcement (CET) Shadow Stack
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GFNI = CPUFeature(1u) << 104u, // Galois Field Instructions
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VAES = CPUFeature(1u) << 105u, // Vector AES instruction set (VEX-256/EVEX)
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VPCLMULQDQ = CPUFeature(1u) << 106u, // CLMUL instruction set (VEX-256/EVEX)
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AVX512_VNNI = CPUFeature(1u) << 107u, // AVX-512 Vector Neural Network Instructions
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AVX512_BITALG = CPUFeature(1u) << 108u, // AVX-512 BITALG Instructions
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TME_EN = CPUFeature(1u) << 109u, // IA32_TME related MSRs are supported
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AVX512_VPOPCNTDQ = CPUFeature(1u) << 110u, // AVX-512 Vector Population Count Double and Quad-word
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/* ECX Bit 15 */ // Reserved
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INTEL_5_LEVEL_PAGING = CPUFeature(1u) << 112u, // Intel 5-Level Paging
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RDPID = CPUFeature(1u) << 113u, // RDPID Instruction
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KL = CPUFeature(1u) << 114u, // Key Locker
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/* ECX Bit 24 */ // Reserved
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CLDEMOTE = CPUFeature(1u) << 116u, // Cache Line Demote
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/* ECX Bit 26 */ // Reserved
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MOVDIRI = CPUFeature(1u) << 118u, // MOVDIRI Instruction
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MOVDIR64B = CPUFeature(1u) << 119u, // MOVDIR64B Instruction
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ENQCMD = CPUFeature(1u) << 120u, // ENQCMD Instruction
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SGX_LC = CPUFeature(1u) << 121u, // SGX Launch Configuration
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PKS = CPUFeature(1u) << 122u, // Protection Keys for Supervisor-Mode Pages
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/* EAX=7, EDX */ //
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/* ECX Bit 0-1 */ // Reserved
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AVX512_4VNNIW = CPUFeature(1u) << 125u, // AVX-512 4-register Neural Network Instructions
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AVX512_4FMAPS = CPUFeature(1u) << 126u, // AVX-512 4-register Multiply Accumulation Single precision
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FSRM = CPUFeature(1u) << 127u, // Fast Short REP MOVSB
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/* ECX Bit 5-7 */ // Reserved
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AVX512_VP2INTERSECT = CPUFeature(1u) << 131u, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
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SRBDS_CTRL = CPUFeature(1u) << 132u, // Special Register Buffer Data Sampling Mitigations
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MD_CLEAR = CPUFeature(1u) << 133u, // VERW instruction clears CPU buffers
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RTM_ALWAYS_ABORT = CPUFeature(1u) << 134u, // All TSX transactions are aborted
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/* ECX Bit 12 */ // Reserved
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TSX_FORCE_ABORT = CPUFeature(1u) << 136u, // TSX_FORCE_ABORT MSR
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SERIALIZE = CPUFeature(1u) << 137u, // Serialize instruction execution
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HYBRID = CPUFeature(1u) << 138u, // Mixture of CPU types in processor topology
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TSXLDTRK = CPUFeature(1u) << 139u, // TSX suspend load address tracking
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/* ECX Bit 17 */ // Reserved
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PCONFIG = CPUFeature(1u) << 141u, // Platform configuration (Memory Encryption Technologies Instructions)
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LBR = CPUFeature(1u) << 142u, // Architectural Last Branch Records
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CET_IBT = CPUFeature(1u) << 143u, // Control flow enforcement (CET) indirect branch tracking
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/* ECX Bit 21 */ // Reserved
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AMX_BF16 = CPUFeature(1u) << 145u, // Tile computation on bfloat16 numbers
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AVX512_FP16 = CPUFeature(1u) << 146u, // AVX512-FP16 half-precision floating-point instructions
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AMX_TILE = CPUFeature(1u) << 147u, // Tile architecture
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AMX_INT8 = CPUFeature(1u) << 148u, // Tile computation on 8-bit integers
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SPEC_CTRL = CPUFeature(1u) << 149u, // Speculation Control
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STIBP = CPUFeature(1u) << 150u, // Single Thread Indirect Branch Predictor
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L1D_FLUSH = CPUFeature(1u) << 151u, // IA32_FLUSH_CMD MSR
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IA32_ARCH_CAPABILITIES = CPUFeature(1u) << 152u, // IA32_ARCH_CAPABILITIES MSR
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IA32_CORE_CAPABILITIES = CPUFeature(1u) << 153u, // IA32_CORE_CAPABILITIES MSR
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SSBD = CPUFeature(1u) << 154u, // Speculative Store Bypass Disable
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/* EAX=80000001h, EDX */ //
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SYSCALL = CPUFeature(1u) << 68u, // SYSCALL/SYSRET Instructions
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NX = CPUFeature(1u) << 69u, // NX bit
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RDTSCP = CPUFeature(1u) << 70u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 71u, // Long Mode
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SYSCALL = CPUFeature(1u) << 155u, // SYSCALL/SYSRET Instructions
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NX = CPUFeature(1u) << 156u, // NX bit
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RDTSCP = CPUFeature(1u) << 157u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 158u, // Long Mode
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/* EAX=80000007h, EDX */ //
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CONSTANT_TSC = CPUFeature(1u) << 72u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 73u, // Invariant TSC
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__End = CPUFeature(1u) << 127u);
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CONSTANT_TSC = CPUFeature(1u) << 159u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 160u, // Invariant TSC
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__End = CPUFeature(1u) << 255u);
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StringView cpu_feature_to_string_view(CPUFeature::Type const&);
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@ -134,14 +134,167 @@ StringView cpu_feature_to_string_view(CPUFeature::Type const& feature)
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return "ia64"sv;
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if (feature == CPUFeature::PBE)
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return "pbe"sv;
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if (feature == CPUFeature::FSGSBASE)
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return "fsgsbase"sv;
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if (feature == CPUFeature::TSC_ADJUST)
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return "tsc_adjust"sv;
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if (feature == CPUFeature::SGX)
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return "sgx"sv;
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if (feature == CPUFeature::BMI1)
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return "bmi1"sv;
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if (feature == CPUFeature::HLE)
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return "hle"sv;
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if (feature == CPUFeature::AVX2)
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return "avx2"sv;
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if (feature == CPUFeature::FDP_EXCPTN_ONLY)
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return "fdp_excptn_only"sv;
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if (feature == CPUFeature::SMEP)
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return "smep"sv;
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if (feature == CPUFeature::BMI2)
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return "bmi2"sv;
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if (feature == CPUFeature::ERMS)
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return "erms"sv;
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if (feature == CPUFeature::INVPCID)
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return "invpcid"sv;
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if (feature == CPUFeature::RTM)
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return "rtm"sv;
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if (feature == CPUFeature::PQM)
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return "pqm"sv;
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if (feature == CPUFeature::ZERO_FCS_FDS)
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return "zero_fcs_fds"sv;
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if (feature == CPUFeature::MPX)
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return "mpx"sv;
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if (feature == CPUFeature::PQE)
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return "pqe"sv;
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if (feature == CPUFeature::AVX512_F)
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return "avx512_f"sv;
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if (feature == CPUFeature::AVX512_DQ)
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return "avx512_dq"sv;
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if (feature == CPUFeature::RDSEED)
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return "rdseed"sv;
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if (feature == CPUFeature::ADX)
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return "adx"sv;
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if (feature == CPUFeature::SMAP)
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return "smap"sv;
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if (feature == CPUFeature::AVX512_IFMA)
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return "avx512_ifma"sv;
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if (feature == CPUFeature::PCOMMIT)
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return "pcommit"sv;
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if (feature == CPUFeature::CLFLUSHOPT)
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return "clflushopt"sv;
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if (feature == CPUFeature::CLWB)
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return "clwb"sv;
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if (feature == CPUFeature::INTEL_PT)
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return "intel_pt"sv;
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if (feature == CPUFeature::AVX512_PF)
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return "avx512_pf"sv;
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if (feature == CPUFeature::AVX512_ER)
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return "avx512_er"sv;
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if (feature == CPUFeature::AVX512_CD)
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return "avx512_cd"sv;
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if (feature == CPUFeature::SHA)
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return "sha"sv;
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if (feature == CPUFeature::AVX512_BW)
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return "avx512_bw"sv;
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if (feature == CPUFeature::AVX512_VL)
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return "avx512_vl"sv;
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if (feature == CPUFeature::PREFETCHWT1)
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return "prefetchwt1"sv;
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if (feature == CPUFeature::AVX512_VBMI)
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return "avx512_vbmi"sv;
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if (feature == CPUFeature::UMIP)
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return "umip"sv;
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if (feature == CPUFeature::PKU)
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return "pku"sv;
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if (feature == CPUFeature::OSPKU)
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return "ospku"sv;
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if (feature == CPUFeature::WAITPKG)
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return "waitpkg"sv;
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if (feature == CPUFeature::AVX512_VBMI2)
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return "avx512_vbmi2"sv;
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if (feature == CPUFeature::CET_SS)
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return "cet_ss"sv;
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if (feature == CPUFeature::GFNI)
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return "gfni"sv;
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if (feature == CPUFeature::VAES)
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return "vaes"sv;
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if (feature == CPUFeature::VPCLMULQDQ)
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return "vpclmulqdq"sv;
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if (feature == CPUFeature::AVX512_VNNI)
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return "avx512_vnni"sv;
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if (feature == CPUFeature::AVX512_BITALG)
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return "avx512_bitalg"sv;
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if (feature == CPUFeature::TME_EN)
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return "tme_en"sv;
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if (feature == CPUFeature::AVX512_VPOPCNTDQ)
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return "avx512_vpopcntdq"sv;
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if (feature == CPUFeature::INTEL_5_LEVEL_PAGING)
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return "intel_5_level_paging"sv;
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if (feature == CPUFeature::RDPID)
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return "rdpid"sv;
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if (feature == CPUFeature::KL)
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return "kl"sv;
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if (feature == CPUFeature::CLDEMOTE)
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return "cldemote"sv;
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if (feature == CPUFeature::MOVDIRI)
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return "movdiri"sv;
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if (feature == CPUFeature::MOVDIR64B)
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return "movdir64b"sv;
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if (feature == CPUFeature::ENQCMD)
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return "enqcmd"sv;
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if (feature == CPUFeature::SGX_LC)
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return "sgx_lc"sv;
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if (feature == CPUFeature::PKS)
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return "pks"sv;
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if (feature == CPUFeature::AVX512_4VNNIW)
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return "avx512_4vnniw"sv;
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if (feature == CPUFeature::AVX512_4FMAPS)
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return "avx512_4fmaps"sv;
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if (feature == CPUFeature::FSRM)
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return "fsrm"sv;
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if (feature == CPUFeature::AVX512_VP2INTERSECT)
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return "avx512_vp2intersect"sv;
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if (feature == CPUFeature::SRBDS_CTRL)
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return "srbds_ctrl"sv;
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if (feature == CPUFeature::MD_CLEAR)
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return "md_clear"sv;
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if (feature == CPUFeature::RTM_ALWAYS_ABORT)
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return "rtm_always_abort"sv;
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if (feature == CPUFeature::TSX_FORCE_ABORT)
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return "tsx_force_abort"sv;
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if (feature == CPUFeature::SERIALIZE)
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return "serialize"sv;
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if (feature == CPUFeature::HYBRID)
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return "hybrid"sv;
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if (feature == CPUFeature::TSXLDTRK)
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return "tsxldtrk"sv;
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if (feature == CPUFeature::PCONFIG)
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return "pconfig"sv;
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if (feature == CPUFeature::LBR)
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return "lbr"sv;
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if (feature == CPUFeature::CET_IBT)
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return "cet_ibt"sv;
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if (feature == CPUFeature::AMX_BF16)
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return "amx_bf16"sv;
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if (feature == CPUFeature::AVX512_FP16)
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return "avx512_fp16"sv;
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if (feature == CPUFeature::AMX_TILE)
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return "amx_tile"sv;
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if (feature == CPUFeature::AMX_INT8)
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return "amx_int8"sv;
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if (feature == CPUFeature::SPEC_CTRL)
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return "spec_ctrl"sv;
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if (feature == CPUFeature::STIBP)
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return "stibp"sv;
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// NOTE: This is called flush_l1d on Linux, but L1D_FLUSH in the Intel manual.
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if (feature == CPUFeature::L1D_FLUSH)
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return "l1d_flush"sv;
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if (feature == CPUFeature::IA32_ARCH_CAPABILITIES)
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return "ia32_arch_capabilities"sv;
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if (feature == CPUFeature::IA32_CORE_CAPABILITIES)
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return "ia32_code_capabilities"sv;
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if (feature == CPUFeature::SSBD)
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return "ssbd"sv;
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if (feature == CPUFeature::SYSCALL)
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return "syscall"sv;
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if (feature == CPUFeature::NX)
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@ -212,14 +212,169 @@ UNMAP_AFTER_INIT void Processor::cpu_detect()
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m_features |= CPUFeature::PBE;
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CPUID extended_features(0x7);
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if (extended_features.ebx() & (1 << 0))
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m_features |= CPUFeature::FSGSBASE;
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if (extended_features.ebx() & (1 << 1))
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m_features |= CPUFeature::TSC_ADJUST;
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if (extended_features.ebx() & (1 << 2))
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m_features |= CPUFeature::SGX;
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if (extended_features.ebx() & (1 << 3))
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m_features |= CPUFeature::BMI1;
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if (extended_features.ebx() & (1 << 4))
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m_features |= CPUFeature::HLE;
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if (extended_features.ebx() & (1 << 5))
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m_features |= CPUFeature::AVX2;
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if (extended_features.ebx() & (1 << 6))
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m_features |= CPUFeature::FDP_EXCPTN_ONLY;
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if (extended_features.ebx() & (1 << 7))
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m_features |= CPUFeature::SMEP;
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if (extended_features.ebx() & (1 << 8))
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m_features |= CPUFeature::BMI2;
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if (extended_features.ebx() & (1 << 9))
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m_features |= CPUFeature::ERMS;
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if (extended_features.ebx() & (1 << 10))
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m_features |= CPUFeature::INVPCID;
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if (extended_features.ebx() & (1 << 11))
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m_features |= CPUFeature::RTM;
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if (extended_features.ebx() & (1 << 12))
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m_features |= CPUFeature::PQM;
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if (extended_features.ebx() & (1 << 13))
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m_features |= CPUFeature::ZERO_FCS_FDS;
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if (extended_features.ebx() & (1 << 14))
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m_features |= CPUFeature::MPX;
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if (extended_features.ebx() & (1 << 15))
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m_features |= CPUFeature::PQE;
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if (extended_features.ebx() & (1 << 16))
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m_features |= CPUFeature::AVX512_F;
|
||||
if (extended_features.ebx() & (1 << 17))
|
||||
m_features |= CPUFeature::AVX512_DQ;
|
||||
if (extended_features.ebx() & (1 << 18))
|
||||
m_features |= CPUFeature::RDSEED;
|
||||
if (extended_features.ebx() & (1 << 19))
|
||||
m_features |= CPUFeature::ADX;
|
||||
if (extended_features.ebx() & (1 << 20))
|
||||
m_features |= CPUFeature::SMAP;
|
||||
if (extended_features.ebx() & (1 << 21))
|
||||
m_features |= CPUFeature::AVX512_IFMA;
|
||||
if (extended_features.ebx() & (1 << 22))
|
||||
m_features |= CPUFeature::PCOMMIT;
|
||||
if (extended_features.ebx() & (1 << 23))
|
||||
m_features |= CPUFeature::CLFLUSHOPT;
|
||||
if (extended_features.ebx() & (1 << 24))
|
||||
m_features |= CPUFeature::CLWB;
|
||||
if (extended_features.ebx() & (1 << 25))
|
||||
m_features |= CPUFeature::INTEL_PT;
|
||||
if (extended_features.ebx() & (1 << 26))
|
||||
m_features |= CPUFeature::AVX512_PF;
|
||||
if (extended_features.ebx() & (1 << 27))
|
||||
m_features |= CPUFeature::AVX512_ER;
|
||||
if (extended_features.ebx() & (1 << 28))
|
||||
m_features |= CPUFeature::AVX512_CD;
|
||||
if (extended_features.ebx() & (1 << 29))
|
||||
m_features |= CPUFeature::SHA;
|
||||
if (extended_features.ebx() & (1 << 30))
|
||||
m_features |= CPUFeature::AVX512_BW;
|
||||
if (extended_features.ebx() & (1 << 31))
|
||||
m_features |= CPUFeature::AVX512_VL;
|
||||
|
||||
if (extended_features.ecx() & (1 << 0))
|
||||
m_features |= CPUFeature::PREFETCHWT1;
|
||||
if (extended_features.ecx() & (1 << 1))
|
||||
m_features |= CPUFeature::AVX512_VBMI;
|
||||
if (extended_features.ecx() & (1 << 2))
|
||||
m_features |= CPUFeature::UMIP;
|
||||
if (extended_features.ecx() & (1 << 3))
|
||||
m_features |= CPUFeature::PKU;
|
||||
if (extended_features.ecx() & (1 << 4))
|
||||
m_features |= CPUFeature::OSPKU;
|
||||
if (extended_features.ecx() & (1 << 5))
|
||||
m_features |= CPUFeature::WAITPKG;
|
||||
if (extended_features.ecx() & (1 << 6))
|
||||
m_features |= CPUFeature::AVX512_VBMI2;
|
||||
if (extended_features.ecx() & (1 << 7))
|
||||
m_features |= CPUFeature::CET_SS;
|
||||
if (extended_features.ecx() & (1 << 8))
|
||||
m_features |= CPUFeature::GFNI;
|
||||
if (extended_features.ecx() & (1 << 9))
|
||||
m_features |= CPUFeature::VAES;
|
||||
if (extended_features.ecx() & (1 << 10))
|
||||
m_features |= CPUFeature::VPCLMULQDQ;
|
||||
if (extended_features.ecx() & (1 << 11))
|
||||
m_features |= CPUFeature::AVX512_VNNI;
|
||||
if (extended_features.ecx() & (1 << 12))
|
||||
m_features |= CPUFeature::AVX512_BITALG;
|
||||
if (extended_features.ecx() & (1 << 13))
|
||||
m_features |= CPUFeature::TME_EN;
|
||||
if (extended_features.ecx() & (1 << 14))
|
||||
m_features |= CPUFeature::AVX512_VPOPCNTDQ;
|
||||
if (extended_features.ecx() & (1 << 16))
|
||||
m_features |= CPUFeature::INTEL_5_LEVEL_PAGING;
|
||||
if (extended_features.ecx() & (1 << 22))
|
||||
m_features |= CPUFeature::RDPID;
|
||||
if (extended_features.ecx() & (1 << 23))
|
||||
m_features |= CPUFeature::KL;
|
||||
if (extended_features.ecx() & (1 << 25))
|
||||
m_features |= CPUFeature::CLDEMOTE;
|
||||
if (extended_features.ecx() & (1 << 27))
|
||||
m_features |= CPUFeature::MOVDIRI;
|
||||
if (extended_features.ecx() & (1 << 28))
|
||||
m_features |= CPUFeature::MOVDIR64B;
|
||||
if (extended_features.ecx() & (1 << 29))
|
||||
m_features |= CPUFeature::ENQCMD;
|
||||
if (extended_features.ecx() & (1 << 30))
|
||||
m_features |= CPUFeature::SGX_LC;
|
||||
if (extended_features.ecx() & (1 << 31))
|
||||
m_features |= CPUFeature::PKS;
|
||||
|
||||
if (extended_features.edx() & (1 << 2))
|
||||
m_features |= CPUFeature::AVX512_4VNNIW;
|
||||
if (extended_features.edx() & (1 << 3))
|
||||
m_features |= CPUFeature::AVX512_4FMAPS;
|
||||
if (extended_features.edx() & (1 << 4))
|
||||
m_features |= CPUFeature::FSRM;
|
||||
if (extended_features.edx() & (1 << 8))
|
||||
m_features |= CPUFeature::AVX512_VP2INTERSECT;
|
||||
if (extended_features.edx() & (1 << 9))
|
||||
m_features |= CPUFeature::SRBDS_CTRL;
|
||||
if (extended_features.edx() & (1 << 10))
|
||||
m_features |= CPUFeature::MD_CLEAR;
|
||||
if (extended_features.edx() & (1 << 11))
|
||||
m_features |= CPUFeature::RTM_ALWAYS_ABORT;
|
||||
if (extended_features.edx() & (1 << 13))
|
||||
m_features |= CPUFeature::TSX_FORCE_ABORT;
|
||||
if (extended_features.edx() & (1 << 14))
|
||||
m_features |= CPUFeature::SERIALIZE;
|
||||
if (extended_features.edx() & (1 << 15))
|
||||
m_features |= CPUFeature::HYBRID;
|
||||
if (extended_features.edx() & (1 << 16))
|
||||
m_features |= CPUFeature::TSXLDTRK;
|
||||
if (extended_features.edx() & (1 << 18))
|
||||
m_features |= CPUFeature::PCONFIG;
|
||||
if (extended_features.edx() & (1 << 19))
|
||||
m_features |= CPUFeature::LBR;
|
||||
if (extended_features.edx() & (1 << 20))
|
||||
m_features |= CPUFeature::CET_IBT;
|
||||
if (extended_features.edx() & (1 << 22))
|
||||
m_features |= CPUFeature::AMX_BF16;
|
||||
if (extended_features.edx() & (1 << 23))
|
||||
m_features |= CPUFeature::AVX512_FP16;
|
||||
if (extended_features.edx() & (1 << 24))
|
||||
m_features |= CPUFeature::AMX_TILE;
|
||||
if (extended_features.edx() & (1 << 25))
|
||||
m_features |= CPUFeature::AMX_INT8;
|
||||
if (extended_features.edx() & (1 << 26))
|
||||
m_features |= CPUFeature::SPEC_CTRL;
|
||||
if (extended_features.edx() & (1 << 27))
|
||||
m_features |= CPUFeature::STIBP;
|
||||
if (extended_features.edx() & (1 << 28))
|
||||
m_features |= CPUFeature::L1D_FLUSH;
|
||||
if (extended_features.edx() & (1 << 29))
|
||||
m_features |= CPUFeature::IA32_ARCH_CAPABILITIES;
|
||||
if (extended_features.edx() & (1 << 30))
|
||||
m_features |= CPUFeature::IA32_CORE_CAPABILITIES;
|
||||
if (extended_features.edx() & (1 << 31))
|
||||
m_features |= CPUFeature::SSBD;
|
||||
|
||||
u32 max_extended_leaf = CPUID(0x80000000).eax();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue