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Kernel/Storage: Move IDE bus master handling code into a separate class
If the user requests to force PIO mode, we just create IDEChannel objects which are capable of sending PIO commands only. However, if the user doesn't force PIO mode, we create BMIDEChannel objects, which are sending DMA commands. This change is somewhat simplifying the code, so each class is supporting its type of operation - PIO or DMA. The PATADiskDevice should not care if DMA is enabled or not. Later on, we could write an IDEChannel class for UDMA modes, that are available and documented on Intel specifications for their IDE controllers.
This commit is contained in:
Liav A
Andreas Kling
parent
dfb6b296cf
commit
833a6bd047
Notes:
sideshowbarker
2024-07-18 21:02:02 +09:00
Author: https://github.com/supercomputer7 Commit: https://github.com/SerenityOS/serenity/commit/833a6bd047e Pull-request: https://github.com/SerenityOS/serenity/pull/5971
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@ -56,6 +56,7 @@ set(KERNEL_SOURCES
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Storage/AHCIPort.cpp
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Storage/AHCIPortHandler.cpp
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Storage/SATADiskDevice.cpp
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Storage/BMIDEChannel.cpp
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Storage/IDEController.cpp
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Storage/IDEChannel.cpp
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Storage/PATADiskDevice.cpp
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213
Kernel/Storage/BMIDEChannel.cpp
Normal file
213
Kernel/Storage/BMIDEChannel.cpp
Normal file
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@ -0,0 +1,213 @@
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <Kernel/Storage/ATA.h>
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#include <Kernel/Storage/BMIDEChannel.h>
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#include <Kernel/Storage/IDEController.h>
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#include <Kernel/WorkQueue.h>
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namespace Kernel {
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UNMAP_AFTER_INIT NonnullRefPtr<BMIDEChannel> BMIDEChannel::create(const IDEController& ide_controller, IDEChannel::IOAddressGroup io_group, IDEChannel::ChannelType type)
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{
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return adopt(*new BMIDEChannel(ide_controller, io_group, type));
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}
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UNMAP_AFTER_INIT BMIDEChannel::BMIDEChannel(const IDEController& controller, IDEChannel::IOAddressGroup io_group, IDEChannel::ChannelType type)
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: IDEChannel(controller, io_group, type)
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{
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initialize();
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}
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UNMAP_AFTER_INIT void BMIDEChannel::initialize()
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{
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// Let's try to set up DMA transfers.
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PCI::enable_bus_mastering(m_parent_controller->pci_address());
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m_prdt_page = MM.allocate_supervisor_physical_page();
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m_dma_buffer_page = MM.allocate_supervisor_physical_page();
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if (m_dma_buffer_page.is_null() || m_prdt_page.is_null())
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return;
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m_prdt_region = MM.allocate_kernel_region(m_prdt_page->paddr(), PAGE_SIZE, "IDE PRDT", Region::Access::Read | Region::Access::Write);
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m_dma_buffer_region = MM.allocate_kernel_region(m_dma_buffer_page->paddr(), PAGE_SIZE, "IDE DMA region", Region::Access::Read | Region::Access::Write);
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prdt().end_of_table = 0x8000;
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}
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static void print_ide_status(u8 status)
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{
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dbgln("BMIDEChannel: print_ide_status: DRQ={} BSY={}, DRDY={}, DSC={}, DF={}, CORR={}, IDX={}, ERR={}",
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(status & ATA_SR_DRQ) != 0,
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(status & ATA_SR_BSY) != 0,
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(status & ATA_SR_DRDY) != 0,
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(status & ATA_SR_DSC) != 0,
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(status & ATA_SR_DF) != 0,
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(status & ATA_SR_CORR) != 0,
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(status & ATA_SR_IDX) != 0,
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(status & ATA_SR_ERR) != 0);
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}
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void BMIDEChannel::handle_irq(const RegisterState&)
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{
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u8 status = m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
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m_entropy_source.add_random_event(status);
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u8 bstatus = m_io_group.bus_master_base().offset(2).in<u8>();
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if (!(bstatus & 0x4)) {
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// interrupt not from this device, ignore
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dbgln_if(PATA_DEBUG, "BMIDEChannel: ignore interrupt");
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return;
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}
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ScopedSpinLock lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "BMIDEChannel: interrupt: DRQ={}, BSY={}, DRDY={}",
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(status & ATA_SR_DRQ) != 0,
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(status & ATA_SR_BSY) != 0,
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(status & ATA_SR_DRDY) != 0);
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if (!m_current_request) {
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dbgln("BMIDEChannel: IRQ but no pending request!");
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return;
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}
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if (status & ATA_SR_ERR) {
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print_ide_status(status);
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m_device_error = m_io_group.io_base().offset(ATA_REG_ERROR).in<u8>();
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dbgln("BMIDEChannel: Error {:#02x}!", (u8)m_device_error);
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try_disambiguate_error();
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complete_current_request(AsyncDeviceRequest::Failure);
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return;
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}
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m_device_error = 0;
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complete_current_request(AsyncDeviceRequest::Success);
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}
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void BMIDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
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{
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// NOTE: this may be called from the interrupt handler!
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VERIFY(m_current_request);
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VERIFY(m_request_lock.is_locked());
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// Now schedule reading back the buffer as soon as we leave the irq handler.
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// This is important so that we can safely write the buffer back,
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// which could cause page faults. Note that this may be called immediately
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// before Processor::deferred_call_queue returns!
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g_io_work->queue([this, result]() {
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dbgln_if(PATA_DEBUG, "BMIDEChannel::complete_current_request result: {}", (int)result);
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ScopedSpinLock lock(m_request_lock);
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VERIFY(m_current_request);
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auto& request = *m_current_request;
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m_current_request = nullptr;
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if (result == AsyncDeviceRequest::Success) {
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if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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if (!request.write_to_buffer(request.buffer(), m_dma_buffer_region->vaddr().as_ptr(), 512 * request.block_count())) {
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lock.unlock();
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request.complete(AsyncDeviceRequest::MemoryFault);
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return;
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}
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}
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// I read somewhere that this may trigger a cache flush so let's do it.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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}
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lock.unlock();
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request.complete(result);
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});
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}
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void BMIDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
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{
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VERIFY(m_request_lock.is_locked());
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auto& request = *m_current_request;
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auto lba = request.block_index();
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dbgln_if(PATA_DEBUG, "BMIDEChannel::ata_write_sectors_with_dma ({} x {})", lba, request.block_count());
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prdt().offset = m_dma_buffer_page->paddr().get();
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prdt().size = 512 * request.block_count();
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if (!request.read_from_buffer(request.buffer(), m_dma_buffer_region->vaddr().as_ptr(), 512 * request.block_count())) {
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complete_current_request(AsyncDeviceRequest::MemoryFault);
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return;
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}
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VERIFY(prdt().size <= PAGE_SIZE);
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out<u32>(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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ata_access(Direction::Write, slave_request, lba, request.block_count(), capabilities);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x1);
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}
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void BMIDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) const
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{
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if (lba_mode != LBAMode::FortyEightBit) {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA : ATA_CMD_WRITE_DMA);
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} else {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA_EXT : ATA_CMD_WRITE_DMA_EXT);
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}
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}
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void BMIDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
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{
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VERIFY(m_request_lock.is_locked());
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auto& request = *m_current_request;
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auto lba = request.block_index();
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dbgln_if(PATA_DEBUG, "BMIDEChannel::ata_read_sectors_with_dma ({} x {})", lba, request.block_count());
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prdt().offset = m_dma_buffer_page->paddr().get();
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prdt().size = 512 * request.block_count();
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VERIFY(prdt().size <= PAGE_SIZE);
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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// Set transfer direction
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m_io_group.bus_master_base().out<u8>(0x8);
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ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x9);
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}
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}
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73
Kernel/Storage/BMIDEChannel.h
Normal file
73
Kernel/Storage/BMIDEChannel.h
Normal file
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/OwnPtr.h>
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#include <Kernel/Storage/IDEChannel.h>
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namespace Kernel {
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class AsyncBlockDeviceRequest;
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struct [[gnu::packed]] PhysicalRegionDescriptor {
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u32 offset;
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u16 size { 0 };
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u16 end_of_table { 0 };
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};
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class IDEController;
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class BMIDEChannel final : public IDEChannel {
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friend class IDEController;
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friend class PATADiskDevice;
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public:
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static NonnullRefPtr<BMIDEChannel> create(const IDEController&, IDEChannel::IOAddressGroup, IDEChannel::ChannelType type);
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virtual ~BMIDEChannel() override {};
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virtual bool is_dma_enabled() const override { return true; };
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private:
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BMIDEChannel(const IDEController&, IDEChannel::IOAddressGroup, IDEChannel::ChannelType type);
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void initialize();
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void complete_current_request(AsyncDeviceRequest::RequestResult);
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//^ IRQHandler
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virtual void handle_irq(const RegisterState&) override;
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//* IDEChannel
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virtual void send_ata_io_command(LBAMode lba_mode, Direction direction) const;
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virtual void ata_read_sectors(bool, u16);
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virtual void ata_write_sectors(bool, u16);
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PhysicalRegionDescriptor& prdt() { return *reinterpret_cast<PhysicalRegionDescriptor*>(m_prdt_region->vaddr().as_ptr()); }
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OwnPtr<Region> m_prdt_region;
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OwnPtr<Region> m_dma_buffer_region;
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RefPtr<PhysicalPage> m_prdt_page;
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RefPtr<PhysicalPage> m_dma_buffer_page;
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};
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}
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@ -27,7 +27,6 @@
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#include <AK/ByteBuffer.h>
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#include <AK/Singleton.h>
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#include <AK/StringView.h>
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#include <Kernel/FileSystem/ProcFS.h>
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#include <Kernel/IO.h>
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#include <Kernel/Process.h>
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#include <Kernel/Storage/ATA.h>
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@ -45,9 +44,9 @@ namespace Kernel {
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#define PCI_Mass_Storage_Class 0x1
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#define PCI_IDE_Controller_Subclass 0x1
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
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{
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return adopt(*new IDEChannel(controller, io_group, type, force_pio));
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return adopt(*new IDEChannel(controller, io_group, type));
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}
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RefPtr<StorageDevice> IDEChannel::master_device() const
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@ -60,7 +59,7 @@ RefPtr<StorageDevice> IDEChannel::slave_device() const
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return m_slave;
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
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: IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
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, m_channel_type(type)
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, m_io_group(io_group)
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@ -69,15 +68,16 @@ UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddre
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disable_irq();
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// FIXME: The device may not be capable of DMA.
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m_dma_enabled.resource() = !force_pio;
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ProcFS::add_sys_bool("ide_dma", m_dma_enabled);
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initialize(force_pio);
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dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base());
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m_parent_controller->enable_pin_based_interrupts();
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detect_disks();
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// Note: calling to detect_disks could generate an interrupt, clear it if that's the case
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clear_pending_interrupts();
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enable_irq();
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}
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void IDEChannel::clear_pending_interrupts() const
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@ -89,7 +89,7 @@ UNMAP_AFTER_INIT IDEChannel::~IDEChannel()
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{
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}
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void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, bool is_slave, u16 capabilities)
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void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool is_slave, u16 capabilities)
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{
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ScopedSpinLock lock(m_request_lock);
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@ -97,20 +97,12 @@ void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, b
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m_current_request = &request;
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m_current_request_block_index = 0;
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m_current_request_uses_dma = use_dma;
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m_current_request_flushing_cache = false;
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if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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if (use_dma)
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ata_read_sectors_with_dma(is_slave, capabilities);
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else
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ata_read_sectors(is_slave, capabilities);
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} else {
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if (use_dma)
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ata_write_sectors_with_dma(is_slave, capabilities);
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else
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ata_write_sectors(is_slave, capabilities);
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}
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if (request.request_type() == AsyncBlockDeviceRequest::Read)
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ata_read_sectors(is_slave, capabilities);
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else
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ata_write_sectors(is_slave, capabilities);
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}
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void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
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@ -130,46 +122,11 @@ void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult resu
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auto& request = *m_current_request;
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m_current_request = nullptr;
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if (m_current_request_uses_dma) {
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if (result == AsyncDeviceRequest::Success) {
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if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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if (!request.write_to_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
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lock.unlock();
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request.complete(AsyncDeviceRequest::MemoryFault);
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return;
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}
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}
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|
||||
// I read somewhere that this may trigger a cache flush so let's do it.
|
||||
m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
|
||||
}
|
||||
}
|
||||
|
||||
lock.unlock();
|
||||
request.complete(result);
|
||||
});
|
||||
}
|
||||
|
||||
UNMAP_AFTER_INIT void IDEChannel::initialize(bool force_pio)
|
||||
{
|
||||
m_parent_controller->enable_pin_based_interrupts();
|
||||
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base());
|
||||
|
||||
if (force_pio) {
|
||||
dbgln("IDEChannel: Requested to force PIO mode; not setting up DMA");
|
||||
return;
|
||||
}
|
||||
|
||||
// Let's try to set up DMA transfers.
|
||||
PCI::enable_bus_mastering(m_parent_controller->pci_address());
|
||||
m_prdt_page = MM.allocate_supervisor_physical_page();
|
||||
prdt().end_of_table = 0x8000;
|
||||
m_dma_buffer_page = MM.allocate_supervisor_physical_page();
|
||||
}
|
||||
|
||||
static void print_ide_status(u8 status)
|
||||
{
|
||||
dbgln("IDEChannel: print_ide_status: DRQ={} BSY={}, DRDY={}, DSC={}, DF={}, CORR={}, IDX={}, ERR={}",
|
||||
|
|
@ -251,10 +208,6 @@ void IDEChannel::handle_irq(const RegisterState&)
|
|||
return;
|
||||
}
|
||||
m_device_error = 0;
|
||||
if (m_current_request_uses_dma) {
|
||||
complete_current_request(AsyncDeviceRequest::Success);
|
||||
return;
|
||||
}
|
||||
|
||||
// Now schedule reading/writing the buffer as soon as we leave the irq handler.
|
||||
// This is important so that we can safely access the buffers, which could
|
||||
|
|
@ -404,7 +357,7 @@ UNMAP_AFTER_INIT void IDEChannel::detect_disks()
|
|||
}
|
||||
}
|
||||
|
||||
void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8 block_count, u16 capabilities, bool use_dma)
|
||||
void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8 block_count, u16 capabilities)
|
||||
{
|
||||
LBAMode lba_mode;
|
||||
u8 head = 0;
|
||||
|
|
@ -439,48 +392,17 @@ void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8
|
|||
if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
|
||||
break;
|
||||
}
|
||||
|
||||
if (lba_mode != LBAMode::FortyEightBit) {
|
||||
if (use_dma)
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA : ATA_CMD_WRITE_DMA);
|
||||
else
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
|
||||
} else {
|
||||
if (use_dma)
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA_EXT : ATA_CMD_WRITE_DMA_EXT);
|
||||
else
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO_EXT : ATA_CMD_WRITE_PIO_EXT);
|
||||
}
|
||||
send_ata_io_command(lba_mode, direction);
|
||||
enable_irq();
|
||||
}
|
||||
|
||||
void IDEChannel::ata_read_sectors_with_dma(bool slave_request, u16 capabilities)
|
||||
void IDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) const
|
||||
{
|
||||
auto& request = *m_current_request;
|
||||
auto lba = request.block_index();
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors_with_dma ({} x {})", lba, request.block_count());
|
||||
|
||||
prdt().offset = m_dma_buffer_page->paddr();
|
||||
prdt().size = 512 * request.block_count();
|
||||
|
||||
VERIFY(prdt().size <= PAGE_SIZE);
|
||||
|
||||
// Stop bus master
|
||||
m_io_group.bus_master_base().out<u8>(0);
|
||||
|
||||
// Write the PRDT location
|
||||
m_io_group.bus_master_base().offset(4).out(m_prdt_page->paddr().get());
|
||||
|
||||
// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
|
||||
m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
|
||||
|
||||
// Set transfer direction
|
||||
m_io_group.bus_master_base().out<u8>(0x8);
|
||||
|
||||
ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, true);
|
||||
|
||||
// Start bus master
|
||||
m_io_group.bus_master_base().out<u8>(0x9);
|
||||
if (lba_mode != LBAMode::FortyEightBit) {
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
|
||||
} else {
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO_EXT : ATA_CMD_WRITE_PIO_EXT);
|
||||
}
|
||||
}
|
||||
|
||||
bool IDEChannel::ata_do_read_sector()
|
||||
|
|
@ -511,38 +433,7 @@ void IDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
|
|||
auto lba = request.block_index();
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel: Reading {} sector(s) @ LBA {}", request.block_count(), lba);
|
||||
|
||||
ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, false);
|
||||
}
|
||||
|
||||
void IDEChannel::ata_write_sectors_with_dma(bool slave_request, u16 capabilities)
|
||||
{
|
||||
auto& request = *m_current_request;
|
||||
auto lba = request.block_index();
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel::ata_write_sectors_with_dma ({} x {})", lba, request.block_count());
|
||||
|
||||
prdt().offset = m_dma_buffer_page->paddr();
|
||||
prdt().size = 512 * request.block_count();
|
||||
|
||||
if (!request.read_from_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
|
||||
complete_current_request(AsyncDeviceRequest::MemoryFault);
|
||||
return;
|
||||
}
|
||||
|
||||
VERIFY(prdt().size <= PAGE_SIZE);
|
||||
|
||||
// Stop bus master
|
||||
m_io_group.bus_master_base().out<u8>(0);
|
||||
|
||||
// Write the PRDT location
|
||||
m_io_group.bus_master_base().offset(4).out<u32>(m_prdt_page->paddr().get());
|
||||
|
||||
// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
|
||||
m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
|
||||
|
||||
ata_access(Direction::Write, slave_request, lba, request.block_count(), capabilities, true);
|
||||
|
||||
// Start bus master
|
||||
m_io_group.bus_master_base().out<u8>(0x1);
|
||||
ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities);
|
||||
}
|
||||
|
||||
void IDEChannel::ata_do_write_sector()
|
||||
|
|
@ -577,7 +468,7 @@ void IDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
|
|||
u32 count = request.block_count();
|
||||
dbgln_if(PATA_DEBUG, "IDEChannel: Writing {} sector(s) @ LBA {}", count, start_sector);
|
||||
|
||||
ata_access(Direction::Write, slave_request, start_sector, request.block_count(), capabilities, false);
|
||||
ata_access(Direction::Write, slave_request, start_sector, request.block_count(), capabilities);
|
||||
ata_do_write_sector();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <AK/OwnPtr.h>
|
||||
#include <AK/RefPtr.h>
|
||||
#include <Kernel/Devices/Device.h>
|
||||
#include <Kernel/IO.h>
|
||||
|
|
@ -53,14 +52,8 @@ namespace Kernel {
|
|||
|
||||
class AsyncBlockDeviceRequest;
|
||||
|
||||
struct PhysicalRegionDescriptor {
|
||||
PhysicalAddress offset;
|
||||
u16 size { 0 };
|
||||
u16 end_of_table { 0 };
|
||||
};
|
||||
|
||||
class IDEController;
|
||||
class IDEChannel final : public RefCounted<IDEChannel>
|
||||
class IDEChannel : public RefCounted<IDEChannel>
|
||||
, public IRQHandler {
|
||||
friend class IDEController;
|
||||
friend class PATADiskDevice;
|
||||
|
|
@ -105,7 +98,7 @@ public:
|
|||
};
|
||||
|
||||
public:
|
||||
static NonnullRefPtr<IDEChannel> create(const IDEController&, IOAddressGroup, ChannelType type, bool force_pio);
|
||||
static NonnullRefPtr<IDEChannel> create(const IDEController&, IOAddressGroup, ChannelType type);
|
||||
virtual ~IDEChannel() override;
|
||||
|
||||
RefPtr<StorageDevice> master_device() const;
|
||||
|
|
@ -113,12 +106,12 @@ public:
|
|||
|
||||
virtual const char* purpose() const override { return "PATA Channel"; }
|
||||
|
||||
virtual bool is_dma_enabled() const { return false; }
|
||||
|
||||
private:
|
||||
IDEChannel(const IDEController&, IOAddressGroup, ChannelType type, bool force_pio);
|
||||
|
||||
//^ IRQHandler
|
||||
virtual void handle_irq(const RegisterState&) override;
|
||||
void complete_current_request(AsyncDeviceRequest::RequestResult);
|
||||
|
||||
protected:
|
||||
enum class LBAMode : u8 {
|
||||
None, // CHS
|
||||
TwentyEightBit,
|
||||
|
|
@ -130,35 +123,34 @@ private:
|
|||
Write,
|
||||
};
|
||||
|
||||
void initialize(bool force_pio);
|
||||
IDEChannel(const IDEController&, IOAddressGroup, ChannelType type);
|
||||
//^ IRQHandler
|
||||
virtual void handle_irq(const RegisterState&) override;
|
||||
|
||||
virtual void send_ata_io_command(LBAMode lba_mode, Direction direction) const;
|
||||
|
||||
virtual void ata_read_sectors(bool, u16);
|
||||
virtual void ata_write_sectors(bool, u16);
|
||||
|
||||
void detect_disks();
|
||||
String channel_type_string() const;
|
||||
|
||||
void try_disambiguate_error();
|
||||
void wait_until_not_busy();
|
||||
|
||||
void start_request(AsyncBlockDeviceRequest&, bool, bool, u16);
|
||||
void complete_current_request(AsyncDeviceRequest::RequestResult);
|
||||
void start_request(AsyncBlockDeviceRequest&, bool, u16);
|
||||
|
||||
void clear_pending_interrupts() const;
|
||||
|
||||
void ata_access(Direction, bool, u64, u8, u16, bool);
|
||||
void ata_read_sectors_with_dma(bool, u16);
|
||||
void ata_read_sectors(bool, u16);
|
||||
void ata_access(Direction, bool, u64, u8, u16);
|
||||
|
||||
bool ata_do_read_sector();
|
||||
void ata_write_sectors_with_dma(bool, u16);
|
||||
void ata_write_sectors(bool, u16);
|
||||
void ata_do_write_sector();
|
||||
|
||||
// Data members
|
||||
ChannelType m_channel_type { ChannelType::Primary };
|
||||
|
||||
volatile u8 m_device_error { 0 };
|
||||
|
||||
PhysicalRegionDescriptor& prdt() { return *reinterpret_cast<PhysicalRegionDescriptor*>(m_prdt_page->paddr().offset(0xc0000000).as_ptr()); }
|
||||
RefPtr<PhysicalPage> m_prdt_page;
|
||||
RefPtr<PhysicalPage> m_dma_buffer_page;
|
||||
Lockable<bool> m_dma_enabled;
|
||||
EntropySource m_entropy_source;
|
||||
|
||||
RefPtr<StorageDevice> m_master;
|
||||
|
|
@ -166,7 +158,6 @@ private:
|
|||
|
||||
AsyncBlockDeviceRequest* m_current_request { nullptr };
|
||||
u32 m_current_request_block_index { 0 };
|
||||
bool m_current_request_uses_dma { false };
|
||||
bool m_current_request_flushing_cache { false };
|
||||
SpinLock<u8> m_request_lock;
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@
|
|||
#include <AK/OwnPtr.h>
|
||||
#include <AK/RefPtr.h>
|
||||
#include <AK/Types.h>
|
||||
#include <Kernel/FileSystem/ProcFS.h>
|
||||
#include <Kernel/Storage/BMIDEChannel.h>
|
||||
#include <Kernel/Storage/IDEController.h>
|
||||
#include <Kernel/Storage/PATADiskDevice.h>
|
||||
|
||||
|
|
@ -87,13 +89,21 @@ UNMAP_AFTER_INIT void IDEController::initialize(bool force_pio)
|
|||
auto bar1 = PCI::get_BAR1(pci_address());
|
||||
auto control_io = (bar1 == 0x1 || bar1 == 0) ? IOAddress(0x3F6) : IOAddress(bar1);
|
||||
|
||||
m_channels.append(IDEChannel::create(*this, { base_io, control_io, bus_master_base }, IDEChannel::ChannelType::Primary, force_pio));
|
||||
if (force_pio)
|
||||
m_channels.append(IDEChannel::create(*this, { base_io, control_io, bus_master_base }, IDEChannel::ChannelType::Primary));
|
||||
else
|
||||
m_channels.append(BMIDEChannel::create(*this, { base_io, control_io, bus_master_base }, IDEChannel::ChannelType::Primary));
|
||||
m_channels[0].enable_irq();
|
||||
|
||||
auto bar2 = PCI::get_BAR2(pci_address());
|
||||
base_io = (bar2 == 0x1 || bar2 == 0) ? IOAddress(0x170) : IOAddress(bar2);
|
||||
auto bar3 = PCI::get_BAR3(pci_address());
|
||||
control_io = (bar3 == 0x1 || bar3 == 0) ? IOAddress(0x376) : IOAddress(bar3);
|
||||
m_channels.append(IDEChannel::create(*this, { base_io, control_io, bus_master_base.offset(8) }, IDEChannel::ChannelType::Secondary, force_pio));
|
||||
if (force_pio)
|
||||
m_channels.append(IDEChannel::create(*this, { base_io, control_io, bus_master_base.offset(8) }, IDEChannel::ChannelType::Secondary));
|
||||
else
|
||||
m_channels.append(BMIDEChannel::create(*this, { base_io, control_io, bus_master_base.offset(8) }, IDEChannel::ChannelType::Secondary));
|
||||
m_channels[1].enable_irq();
|
||||
}
|
||||
|
||||
RefPtr<StorageDevice> IDEController::device_by_channel_and_position(u32 index) const
|
||||
|
|
|
|||
|
|
@ -58,8 +58,7 @@ const char* PATADiskDevice::class_name() const
|
|||
|
||||
void PATADiskDevice::start_request(AsyncBlockDeviceRequest& request)
|
||||
{
|
||||
bool use_dma = !m_channel->m_io_group.bus_master_base().is_null() && m_channel->m_dma_enabled.resource();
|
||||
m_channel->start_request(request, use_dma, is_slave(), m_capabilities);
|
||||
m_channel->start_request(request, is_slave(), m_capabilities);
|
||||
}
|
||||
|
||||
String PATADiskDevice::device_name() const
|
||||
|
|
|
|||
Loading…
Reference in a new issue