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Kernel/aarch64: Implement tlb flushing
This initial implementation flushes the complete tlb cache. A FIXME is added to implement the partial tlb flushing.
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parent
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57901a6f62
Notes:
sideshowbarker
2024-07-17 06:30:21 +09:00
Author: https://github.com/FireFox317 Commit: https://github.com/SerenityOS/serenity/commit/57901a6f62 Pull-request: https://github.com/SerenityOS/serenity/pull/15309 Reviewed-by: https://github.com/bgianfo Reviewed-by: https://github.com/bugreport0 Reviewed-by: https://github.com/nico ✅
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@ -41,7 +41,16 @@ void Processor::initialize(u32 cpu)
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void Processor::flush_tlb_local(VirtualAddress, size_t)
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{
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// FIXME: Implement this
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// FIXME: Figure out how to flush a single page
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asm volatile("dsb ishst");
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asm volatile("tlbi vmalle1is");
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asm volatile("dsb ish");
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asm volatile("isb");
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}
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void Processor::flush_tlb(Memory::PageDirectory const*, VirtualAddress vaddr, size_t page_count)
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{
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flush_tlb_local(vaddr, page_count);
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}
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}
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@ -77,10 +77,7 @@ public:
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}
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static void flush_tlb_local(VirtualAddress vaddr, size_t page_count);
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ALWAYS_INLINE static void flush_tlb(Memory::PageDirectory const*, VirtualAddress const&, size_t)
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{
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VERIFY_NOT_REACHED();
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}
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static void flush_tlb(Memory::PageDirectory const*, VirtualAddress, size_t);
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// FIXME: When aarch64 supports multiple cores, return the correct core id here.
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ALWAYS_INLINE static u32 current_id()
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