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LibX86: Add basic x86-64 support
Most of the 64-bit instructions default to 32-bit operands and select 64-bit using REX.W prefixes. Because of that instead of defining new instruction formats, this reuses the 32-bit formats and changes them to take the REX prefixes into account when necessary. Additionally this removes, adds or modifies the instruction descriptors in the 64-bit table, where they are different from 32-bit. Using 'disasm' these changes seem to cover pretty much all of our 64-bit binaries (except for AVX) :^) Note that UserspaceEmulator will need to account for these prefixed versions in its 32-bit instruction handlers before being usable on x86-64.
This commit is contained in:
Simon Wanner
Andreas Kling
parent
735fd5f5db
commit
2ae228dac7
Notes:
sideshowbarker
2024-07-17 06:09:44 +09:00
Author: https://github.com/skyrising Commit: https://github.com/SerenityOS/serenity/commit/2ae228dac7 Pull-request: https://github.com/SerenityOS/serenity/pull/15465 Reviewed-by: https://github.com/ADKaster ✅ Reviewed-by: https://github.com/Hendiadyoin1
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@ -26,7 +26,7 @@ public:
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return Instruction::from_stream(m_stream, OperandSize::Size32, AddressSize::Size32);
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#else
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# if ARCH(X86_64)
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return Instruction::from_stream(m_stream, OperandSize::Size64, AddressSize::Size64);
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return Instruction::from_stream(m_stream, OperandSize::Size32, AddressSize::Size64);
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# else
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dbgln("Unsupported platform");
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return {};
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2022, the SerenityOS developers.
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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@ -32,7 +33,7 @@ static bool opcode_has_register_index(u8 op)
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return false;
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}
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static void build(InstructionDescriptor* table, u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler handler, IsLockPrefixAllowed lock_prefix_allowed)
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static void build_in_table(InstructionDescriptor* table, u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler handler, IsLockPrefixAllowed lock_prefix_allowed)
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{
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InstructionDescriptor& d = table[op];
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@ -221,7 +222,7 @@ static void build_slash(InstructionDescriptor* table, u8 op, u8 slash, char cons
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if (!d.slashes)
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d.slashes = new InstructionDescriptor[8];
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build(d.slashes, slash, mnemonic, format, handler, lock_prefix_allowed);
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build_in_table(d.slashes, slash, mnemonic, format, handler, lock_prefix_allowed);
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}
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static void build_slash_rm(InstructionDescriptor* table, u8 op, u8 slash, u8 rm, char const* mnemonic, InstructionFormat format, InstructionHandler handler)
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@ -242,28 +243,31 @@ static void build_slash_rm(InstructionDescriptor* table, u8 op, u8 slash, u8 rm,
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}
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}
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build(d.slashes, rm & 7, mnemonic, format, handler, LockPrefixNotAllowed);
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build_in_table(d.slashes, rm & 7, mnemonic, format, handler, LockPrefixNotAllowed);
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}
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template<auto table>
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static void build_base(u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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build(table[to_underlying(OperandSize::Size16)], op, mnemonic, format, impl, lock_prefix_allowed);
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build(table[to_underlying(OperandSize::Size32)], op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size16)], op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size32)], op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size64)], op, mnemonic, format, impl, lock_prefix_allowed);
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}
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template<auto table>
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static void build_base(u8 op, char const* mnemonic, InstructionFormat format16, InstructionHandler impl16, InstructionFormat format32, InstructionHandler impl32, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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build(table[to_underlying(OperandSize::Size16)], op, mnemonic, format16, impl16, lock_prefix_allowed);
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build(table[to_underlying(OperandSize::Size32)], op, mnemonic, format32, impl32, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size16)], op, mnemonic, format16, impl16, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size32)], op, mnemonic, format32, impl32, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size64)], op, mnemonic, format32, impl32, lock_prefix_allowed);
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}
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template<auto table>
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static void build_base(u8 op, char const* mnemonic16, InstructionFormat format16, InstructionHandler impl16, char const* mnemonic32, InstructionFormat format32, InstructionHandler impl32, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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build(table[to_underlying(OperandSize::Size16)], op, mnemonic16, format16, impl16, lock_prefix_allowed);
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build(table[to_underlying(OperandSize::Size32)], op, mnemonic32, format32, impl32, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size16)], op, mnemonic16, format16, impl16, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size32)], op, mnemonic32, format32, impl32, lock_prefix_allowed);
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build_in_table(table[to_underlying(OperandSize::Size64)], op, mnemonic32, format32, impl32, lock_prefix_allowed);
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}
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template<auto table>
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@ -271,6 +275,7 @@ static void build_slash_base(u8 op, u8 slash, char const* mnemonic, InstructionF
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{
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build_slash(table[to_underlying(OperandSize::Size16)], op, slash, mnemonic, format, impl, lock_prefix_allowed);
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build_slash(table[to_underlying(OperandSize::Size32)], op, slash, mnemonic, format, impl, lock_prefix_allowed);
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build_slash(table[to_underlying(OperandSize::Size64)], op, slash, mnemonic, format, impl, lock_prefix_allowed);
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}
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template<auto table>
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@ -278,6 +283,7 @@ static void build_slash_base(u8 op, u8 slash, char const* mnemonic, InstructionF
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{
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build_slash(table[to_underlying(OperandSize::Size16)], op, slash, mnemonic, format16, impl16, lock_prefix_allowed);
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build_slash(table[to_underlying(OperandSize::Size32)], op, slash, mnemonic, format32, impl32, lock_prefix_allowed);
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build_slash(table[to_underlying(OperandSize::Size64)], op, slash, mnemonic, format32, impl32, lock_prefix_allowed);
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}
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template<typename... Args>
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@ -308,6 +314,7 @@ static void build_slash_rm(u8 op, u8 slash, u8 rm, char const* mnemonic, Instruc
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{
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build_slash_rm(s_table[to_underlying(OperandSize::Size16)], op, slash, rm, mnemonic, format, impl);
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build_slash_rm(s_table[to_underlying(OperandSize::Size32)], op, slash, rm, mnemonic, format, impl);
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build_slash_rm(s_table[to_underlying(OperandSize::Size64)], op, slash, rm, mnemonic, format, impl);
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}
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static void build_slash_reg(u8 op, u8 slash, char const* mnemonic, InstructionFormat format, InstructionHandler impl)
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@ -320,14 +327,14 @@ static void build_sse_np(u8 op, char const* mnemonic, InstructionFormat format,
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{
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if (s_0f_table[to_underlying(OperandSize::Size32)][op].format == InvalidFormat) {
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build_0f(op, mnemonic, format, impl, lock_prefix_allowed);
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build(s_sse_table_np, op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(s_sse_table_np, op, mnemonic, format, impl, lock_prefix_allowed);
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return;
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}
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if (s_0f_table[to_underlying(OperandSize::Size32)][op].format != __SSE)
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build_0f(op, "__SSE_temp", __SSE, nullptr, lock_prefix_allowed);
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VERIFY(s_0f_table[to_underlying(OperandSize::Size32)][op].format == __SSE);
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build(s_sse_table_np, op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(s_sse_table_np, op, mnemonic, format, impl, lock_prefix_allowed);
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}
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static void build_sse_66(u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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@ -335,7 +342,7 @@ static void build_sse_66(u8 op, char const* mnemonic, InstructionFormat format,
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if (s_0f_table[to_underlying(OperandSize::Size32)][op].format != __SSE)
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build_0f(op, "__SSE_temp", __SSE, nullptr, lock_prefix_allowed);
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VERIFY(s_0f_table[to_underlying(AddressSize::Size32)][op].format == __SSE);
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build(s_sse_table_66, op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(s_sse_table_66, op, mnemonic, format, impl, lock_prefix_allowed);
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}
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static void build_sse_f3(u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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@ -343,7 +350,7 @@ static void build_sse_f3(u8 op, char const* mnemonic, InstructionFormat format,
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if (s_0f_table[to_underlying(OperandSize::Size32)][op].format != __SSE)
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build_0f(op, "__SSE_temp", __SSE, nullptr, lock_prefix_allowed);
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VERIFY(s_0f_table[to_underlying(OperandSize::Size32)][op].format == __SSE);
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build(s_sse_table_f3, op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(s_sse_table_f3, op, mnemonic, format, impl, lock_prefix_allowed);
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}
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static void build_sse_f2(u8 op, char const* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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@ -353,7 +360,7 @@ static void build_sse_f2(u8 op, char const* mnemonic, InstructionFormat format,
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VERIFY(s_0f_table[to_underlying(OperandSize::Size32)][op].format == __SSE);
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VERIFY(s_sse_table_f2[op].format == InvalidFormat);
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build(s_sse_table_f2, op, mnemonic, format, impl, lock_prefix_allowed);
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build_in_table(s_sse_table_f2, op, mnemonic, format, impl, lock_prefix_allowed);
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}
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static void build_sse_np_slash(u8 op, u8 slash, char const* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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@ -864,6 +871,8 @@ static void build_sse_66_slash(u8 op, u8 slash, char const* mnemonic, Instructio
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build_0f_slash(0x18, 2, "PREFETCHT1", OP_RM8, &Interpreter::PREFETCHT1);
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build_0f_slash(0x18, 3, "PREFETCHT2", OP_RM8, &Interpreter::PREFETCHT2);
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build_0f_slash(0x1f, 0, "NOP", OP_RM32, &Interpreter::NOP);
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// FIXME: Technically NoPrefix (sse_np_slash?)
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build_0f_slash(0xAE, 2, "LDMXCSR", OP_RM32, &Interpreter::LDMXCSR);
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build_0f_slash(0xAE, 3, "STMXCSR", OP_RM32, &Interpreter::STMXCSR);
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@ -1203,11 +1212,59 @@ static void build_sse_66_slash(u8 op, u8 slash, char const* mnemonic, Instructio
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build_0f(0xFD, "PADDW", OP_mm1_mm2m64, &Interpreter::PADDW_mm1_mm2m64);
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build_0f(0xFE, "PADDD", OP_mm1_mm2m64, &Interpreter::PADDD_mm1_mm2m64);
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build_0f(0xFF, "UD0", OP, &Interpreter::UD0);
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// Changes between 32-bit and 64-bit. These are marked with i64/d64/f64 in the Intel manual's opcode tables
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auto* table64 = s_table[to_underlying(OperandSize::Size64)];
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table64[0x06] = {}; // PUSH ES
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table64[0x07] = {}; // POP ES
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table64[0x16] = {}; // PUSH SS
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table64[0x17] = {}; // POP SS
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table64[0x27] = {}; // DAA
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table64[0x37] = {}; // AAA
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for (u8 rex = 0x40; rex < 0x50; rex++)
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table64[rex] = {}; // INC/DEC, replaced by REX prefixes
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for (u8 pushPop = 0x50; pushPop < 0x60; pushPop++)
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table64[pushPop].long_mode_default_64 = true; // PUSH/POP general register
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for (u8 i = 0x60; i < 0x68; i++)
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table64[i] = {}; // PUSHA{D}, POPA{D}, BOUND
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// ARPL replaced by MOVSXD
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build_in_table(table64, 0x63, "MOVSXD", OP_RM32_reg32, nullptr, LockPrefixNotAllowed);
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table64[0x68].long_mode_default_64 = true; // PUSH
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table64[0x6A].long_mode_default_64 = true; // PUSH
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for (u8 jmp = 0x70; jmp < 0x80; jmp++)
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table64[jmp].long_mode_force_64 = true; // Jcc
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table64[0x9A] = {}; // far CALL
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table64[0x9C].long_mode_default_64 = true; // PUSHF/D/Q
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table64[0x9D].long_mode_default_64 = true; // POPF/D/Q
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build_in_table(table64, 0xB8, "MOV", OP_regW_immW, &Interpreter::MOV_reg32_imm32, LockPrefixNotAllowed);
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table64[0xC2].long_mode_force_64 = true; // near RET
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table64[0xC3].long_mode_force_64 = true; // near RET
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table64[0xC4] = {}; // LES
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table64[0xC5] = {}; // LDS
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table64[0xC9].long_mode_default_64 = true; // LEAVE
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table64[0xCE].long_mode_default_64 = true; // INTO
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table64[0xD4] = {}; // AAM
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table64[0xD5] = {}; // AAD
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for (u8 i = 0; i < 4; i++) {
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table64[0xE0 | i].long_mode_force_64 = true; // LOOPN[EZ], LOOP[EZ], LOOP, JrCXZ
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table64[0xE8 | i].long_mode_force_64 = true; // near CALL, {near,far,short} JMP
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}
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auto* table64_0f = s_0f_table[to_underlying(OperandSize::Size64)];
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build_in_table(table64_0f, 0x05, "SYSCALL", OP, nullptr, LockPrefixNotAllowed);
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build_in_table(table64_0f, 0x07, "SYSRET", OP, nullptr, LockPrefixNotAllowed);
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for (u8 i = 0x80; i < 0x90; i++)
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table64_0f[i].long_mode_force_64 = true; // Jcc
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table64_0f[0xA0].long_mode_default_64 = true; // PUSH FS
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table64_0f[0xA1].long_mode_default_64 = true; // POP FS
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table64_0f[0xA8].long_mode_default_64 = true; // PUSH GS
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table64_0f[0xA9].long_mode_default_64 = true; // POP GS
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}
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static StringView register_name(RegisterIndex8);
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static StringView register_name(RegisterIndex16);
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static StringView register_name(RegisterIndex32);
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static StringView register_name(RegisterIndex64);
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static StringView register_name(FpuRegisterIndex);
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static StringView register_name(SegmentRegister);
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static StringView register_name(MMXRegisterIndex);
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@ -1228,6 +1285,11 @@ StringView Instruction::reg32_name() const
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return register_name(static_cast<RegisterIndex32>(register_index()));
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}
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StringView Instruction::reg64_name() const
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{
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return register_name(static_cast<RegisterIndex64>(register_index()));
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}
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String MemoryOrRegisterReference::to_string_o8(Instruction const& insn) const
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{
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if (is_register())
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@ -1249,6 +1311,13 @@ String MemoryOrRegisterReference::to_string_o32(Instruction const& insn) const
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return String::formatted("[{}]", to_string(insn));
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}
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String MemoryOrRegisterReference::to_string_o64(Instruction const& insn) const
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{
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if (is_register())
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return register_name(reg64());
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return String::formatted("[{}]", to_string(insn));
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}
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String MemoryOrRegisterReference::to_string_fpu_reg() const
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{
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VERIFY(is_register());
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@ -1312,7 +1381,7 @@ String MemoryOrRegisterReference::to_string(Instruction const& insn) const
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case AddressSize::Size64:
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return to_string_a64();
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case AddressSize::Size32:
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return to_string_a32();
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return insn.mode() == ProcessorMode::Long ? to_string_a64() : to_string_a32();
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case AddressSize::Size16:
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return to_string_a16();
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}
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@ -1371,7 +1440,7 @@ String MemoryOrRegisterReference::to_string_a16() const
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return String::formatted("{}{}", base, displacement_string);
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}
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String MemoryOrRegisterReference::sib_to_string(ProcessorMode) const
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String MemoryOrRegisterReference::sib_to_string(ProcessorMode mode) const
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{
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String scale;
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String index;
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@ -1390,16 +1459,16 @@ String MemoryOrRegisterReference::sib_to_string(ProcessorMode) const
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break;
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}
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if (m_sib_index != 4)
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index = register_name(RegisterIndex32(m_sib_index));
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index = mode == ProcessorMode::Long ? register_name(RegisterIndex64(m_sib_index)) : register_name(RegisterIndex32(m_sib_index));
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if (m_sib_base == 5) {
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switch (m_reg) {
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case 1:
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case 2:
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base = "ebp";
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base = mode == ProcessorMode::Long ? "rbp" : "ebp";
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break;
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}
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} else {
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base = register_name(RegisterIndex32(m_sib_base));
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base = mode == ProcessorMode::Long ? register_name(RegisterIndex64(m_sib_base)) : register_name(RegisterIndex32(m_sib_base));
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}
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StringBuilder builder;
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if (base.is_empty()) {
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@ -1418,7 +1487,7 @@ String MemoryOrRegisterReference::sib_to_string(ProcessorMode) const
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String MemoryOrRegisterReference::to_string_a64() const
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{
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if (is_register())
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return register_name(static_cast<RegisterIndex32>(m_register_index));
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return register_name(static_cast<RegisterIndex64>(m_register_index));
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bool has_displacement = false;
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switch (mod()) {
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@ -1436,7 +1505,7 @@ String MemoryOrRegisterReference::to_string_a64() const
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switch (m_rm) {
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case 5:
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if (mod() == 0)
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base = String::formatted("{:#08x}", m_displacement32);
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base = "rip";
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else
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base = "rbp";
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break;
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@ -1444,7 +1513,7 @@ String MemoryOrRegisterReference::to_string_a64() const
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base = sib_to_string(ProcessorMode::Long);
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break;
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default:
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base = register_name(RegisterIndex32(m_rm));
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base = register_name(RegisterIndex64(m_rm));
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}
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if (!has_displacement)
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|
|
@ -1583,9 +1652,13 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, SymbolP
|
|||
|
||||
auto append_rm8 = [&] { builder.append(m_modrm.to_string_o8(*this)); };
|
||||
auto append_rm16 = [&] { builder.append(m_modrm.to_string_o16(*this)); };
|
||||
auto append_rm32 = [&] { builder.append(m_modrm.to_string_o32(*this)); };
|
||||
// FIXME: Registers in long-mode
|
||||
auto append_rm64 = [&] { builder.append(m_modrm.to_string_o32(*this)); };
|
||||
auto append_rm32 = [&] {
|
||||
if (m_operand_size == OperandSize::Size64)
|
||||
builder.append(m_modrm.to_string_o64(*this));
|
||||
else
|
||||
builder.append(m_modrm.to_string_o32(*this));
|
||||
};
|
||||
auto append_rm64 = [&] { builder.append(m_modrm.to_string_o64(*this)); };
|
||||
auto append_fpu_reg = [&] { builder.append(m_modrm.to_string_fpu_reg()); };
|
||||
auto append_fpu_mem = [&] { builder.append(m_modrm.to_string_fpu_mem(*this)); };
|
||||
auto append_fpu_ax16 = [&] { builder.append(m_modrm.to_string_fpu_ax16()); };
|
||||
|
|
@ -1609,16 +1682,24 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, SymbolP
|
|||
};
|
||||
auto append_reg8 = [&] { builder.append(reg8_name()); };
|
||||
auto append_reg16 = [&] { builder.append(reg16_name()); };
|
||||
auto append_reg32 = [&] { builder.append(reg32_name()); };
|
||||
auto append_reg32 = [&] {
|
||||
if (m_operand_size == OperandSize::Size64)
|
||||
builder.append(reg64_name());
|
||||
else
|
||||
builder.append(reg32_name());
|
||||
};
|
||||
auto append_seg = [&] { builder.append(register_name(segment_register())); };
|
||||
auto append_creg = [&] { builder.appendff("cr{}", register_index()); };
|
||||
auto append_dreg = [&] { builder.appendff("dr{}", register_index()); };
|
||||
auto append_relative_addr = [&] {
|
||||
if (m_address_size == AddressSize::Size32) {
|
||||
formatted_address(origin + 6, x32, i32(imm32()));
|
||||
} else if (m_address_size == AddressSize::Size16) {
|
||||
switch (m_address_size) {
|
||||
case AddressSize::Size16:
|
||||
formatted_address(origin + 4, x32, i32(imm16()));
|
||||
} else {
|
||||
break;
|
||||
case AddressSize::Size32:
|
||||
formatted_address(origin + 6, x32, i32(imm32()));
|
||||
break;
|
||||
default:
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
};
|
||||
|
|
@ -1653,7 +1734,9 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, SymbolP
|
|||
auto append = [&](auto content) { builder.append(content); };
|
||||
auto append_moff = [&] {
|
||||
builder.append('[');
|
||||
if (m_address_size == AddressSize::Size32) {
|
||||
if (m_address_size == AddressSize::Size64) {
|
||||
append_imm64();
|
||||
} else if (m_address_size == AddressSize::Size32) {
|
||||
append_imm32();
|
||||
} else if (m_address_size == AddressSize::Size16) {
|
||||
append_imm16();
|
||||
|
|
@ -2428,20 +2511,26 @@ StringView register_name(SegmentRegister index)
|
|||
|
||||
StringView register_name(RegisterIndex8 register_index)
|
||||
{
|
||||
static constexpr StringView names[] = { "al"sv, "cl"sv, "dl"sv, "bl"sv, "ah"sv, "ch"sv, "dh"sv, "bh"sv };
|
||||
return names[register_index & 7];
|
||||
static constexpr StringView names[] = { "al"sv, "cl"sv, "dl"sv, "bl"sv, "ah"sv, "ch"sv, "dh"sv, "bh"sv, "r8b"sv, "r9b"sv, "r10b"sv, "r11b"sv, "r12b"sv, "r13b"sv, "r14b"sv, "r15b"sv };
|
||||
return names[register_index & 15];
|
||||
}
|
||||
|
||||
StringView register_name(RegisterIndex16 register_index)
|
||||
{
|
||||
static constexpr StringView names[] = { "ax"sv, "cx"sv, "dx"sv, "bx"sv, "sp"sv, "bp"sv, "si"sv, "di"sv };
|
||||
return names[register_index & 7];
|
||||
static constexpr StringView names[] = { "ax"sv, "cx"sv, "dx"sv, "bx"sv, "sp"sv, "bp"sv, "si"sv, "di"sv, "r8w"sv, "r9w"sv, "r10w"sv, "r11w"sv, "r12w"sv, "r13w"sv, "r14w"sv, "r15w"sv };
|
||||
return names[register_index & 15];
|
||||
}
|
||||
|
||||
StringView register_name(RegisterIndex32 register_index)
|
||||
{
|
||||
static constexpr StringView names[] = { "eax"sv, "ecx"sv, "edx"sv, "ebx"sv, "esp"sv, "ebp"sv, "esi"sv, "edi"sv };
|
||||
return names[register_index & 7];
|
||||
static constexpr StringView names[] = { "eax"sv, "ecx"sv, "edx"sv, "ebx"sv, "esp"sv, "ebp"sv, "esi"sv, "edi"sv, "r8d"sv, "r9d"sv, "r10d"sv, "r11d"sv, "r12d"sv, "r13d"sv, "r14d"sv, "r15d"sv };
|
||||
return names[register_index & 15];
|
||||
}
|
||||
|
||||
StringView register_name(RegisterIndex64 register_index)
|
||||
{
|
||||
static constexpr StringView names[] = { "rax"sv, "rcx"sv, "rdx"sv, "rbx"sv, "rsp"sv, "rbp"sv, "rsi"sv, "rdi"sv, "r8"sv, "r9"sv, "r10"sv, "r11"sv, "r12"sv, "r13"sv, "r14"sv, "r15"sv };
|
||||
return names[register_index & 15];
|
||||
}
|
||||
|
||||
StringView register_name(FpuRegisterIndex register_index)
|
||||
|
|
@ -2458,8 +2547,8 @@ StringView register_name(MMXRegisterIndex register_index)
|
|||
|
||||
StringView register_name(XMMRegisterIndex register_index)
|
||||
{
|
||||
static constexpr StringView names[] = { "xmm0"sv, "xmm1"sv, "xmm2"sv, "xmm3"sv, "xmm4"sv, "xmm5"sv, "xmm6"sv, "xmm7"sv };
|
||||
return names[register_index & 7];
|
||||
static constexpr StringView names[] = { "xmm0"sv, "xmm1"sv, "xmm2"sv, "xmm3"sv, "xmm4"sv, "xmm5"sv, "xmm6"sv, "xmm7"sv, "xmm8"sv, "xmm9"sv, "xmm10"sv, "xmm11"sv, "xmm12"sv, "xmm13"sv, "xmm14"sv, "xmm15"sv };
|
||||
return names[register_index & 15];
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -226,6 +226,8 @@ struct InstructionDescriptor {
|
|||
bool has_rm { false };
|
||||
unsigned imm1_bytes { 0 };
|
||||
unsigned imm2_bytes { 0 };
|
||||
bool long_mode_default_64 { false };
|
||||
bool long_mode_force_64 { false };
|
||||
|
||||
// Addressed by the 3 REG bits in the MOD-REG-R/M byte.
|
||||
// Some slash instructions have further subgroups when MOD is 11,
|
||||
|
|
@ -233,10 +235,10 @@ struct InstructionDescriptor {
|
|||
// a non-null slashes member that's indexed by the three R/M bits.
|
||||
InstructionDescriptor* slashes { nullptr };
|
||||
|
||||
unsigned imm1_bytes_for_address_size(AddressSize size) const
|
||||
unsigned imm1_bytes_for(AddressSize address_size, OperandSize operand_size) const
|
||||
{
|
||||
if (imm1_bytes == CurrentAddressSize) {
|
||||
switch (size) {
|
||||
switch (address_size) {
|
||||
case AddressSize::Size64:
|
||||
return 8;
|
||||
case AddressSize::Size32:
|
||||
|
|
@ -246,13 +248,24 @@ struct InstructionDescriptor {
|
|||
}
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
if (imm1_bytes == CurrentOperandSize) {
|
||||
switch (operand_size) {
|
||||
case OperandSize::Size64:
|
||||
return 8;
|
||||
case OperandSize::Size32:
|
||||
return 4;
|
||||
case OperandSize::Size16:
|
||||
return 2;
|
||||
}
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
return imm1_bytes;
|
||||
}
|
||||
|
||||
unsigned imm2_bytes_for_address_size(AddressSize size) const
|
||||
unsigned imm2_bytes_for(AddressSize address_size, OperandSize operand_size) const
|
||||
{
|
||||
if (imm2_bytes == CurrentAddressSize) {
|
||||
switch (size) {
|
||||
switch (address_size) {
|
||||
case AddressSize::Size64:
|
||||
return 8;
|
||||
case AddressSize::Size32:
|
||||
|
|
@ -262,6 +275,17 @@ struct InstructionDescriptor {
|
|||
}
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
if (imm2_bytes == CurrentOperandSize) {
|
||||
switch (operand_size) {
|
||||
case OperandSize::Size64:
|
||||
return 8;
|
||||
case OperandSize::Size32:
|
||||
return 4;
|
||||
case OperandSize::Size16:
|
||||
return 2;
|
||||
}
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
return imm2_bytes;
|
||||
}
|
||||
|
||||
|
|
@ -276,6 +300,8 @@ extern InstructionDescriptor s_sse_table_f3[256];
|
|||
|
||||
struct Prefix {
|
||||
enum Op {
|
||||
REX_Mask = 0xf0,
|
||||
REX_Base = 0x40,
|
||||
OperandSizeOverride = 0x66,
|
||||
AddressSizeOverride = 0x67,
|
||||
REP = 0xf3,
|
||||
|
|
@ -304,7 +330,15 @@ enum RegisterIndex8 {
|
|||
RegisterAH,
|
||||
RegisterCH,
|
||||
RegisterDH,
|
||||
RegisterBH
|
||||
RegisterBH,
|
||||
RegisterR8B,
|
||||
RegisterR9B,
|
||||
RegisterR10B,
|
||||
RegisterR11B,
|
||||
RegisterR12B,
|
||||
RegisterR13B,
|
||||
RegisterR14B,
|
||||
RegisterR15B,
|
||||
};
|
||||
|
||||
enum RegisterIndex16 {
|
||||
|
|
@ -315,7 +349,15 @@ enum RegisterIndex16 {
|
|||
RegisterSP,
|
||||
RegisterBP,
|
||||
RegisterSI,
|
||||
RegisterDI
|
||||
RegisterDI,
|
||||
RegisterR8W,
|
||||
RegisterR9W,
|
||||
RegisterR10W,
|
||||
RegisterR11W,
|
||||
RegisterR12W,
|
||||
RegisterR13W,
|
||||
RegisterR14W,
|
||||
RegisterR15W,
|
||||
};
|
||||
|
||||
enum RegisterIndex32 {
|
||||
|
|
@ -326,7 +368,34 @@ enum RegisterIndex32 {
|
|||
RegisterESP,
|
||||
RegisterEBP,
|
||||
RegisterESI,
|
||||
RegisterEDI
|
||||
RegisterEDI,
|
||||
RegisterR8D,
|
||||
RegisterR9D,
|
||||
RegisterR10D,
|
||||
RegisterR11D,
|
||||
RegisterR12D,
|
||||
RegisterR13D,
|
||||
RegisterR14D,
|
||||
RegisterR15D,
|
||||
};
|
||||
|
||||
enum RegisterIndex64 {
|
||||
RegisterRAX = 0,
|
||||
RegisterRCX,
|
||||
RegisterRDX,
|
||||
RegisterRBX,
|
||||
RegisterRSP,
|
||||
RegisterRBP,
|
||||
RegisterRSI,
|
||||
RegisterRDI,
|
||||
RegisterR8,
|
||||
RegisterR9,
|
||||
RegisterR10,
|
||||
RegisterR11,
|
||||
RegisterR12,
|
||||
RegisterR13,
|
||||
RegisterR14,
|
||||
RegisterR15,
|
||||
};
|
||||
|
||||
enum FpuRegisterIndex {
|
||||
|
|
@ -359,7 +428,15 @@ enum XMMRegisterIndex {
|
|||
RegisterXMM4,
|
||||
RegisterXMM5,
|
||||
RegisterXMM6,
|
||||
RegisterXMM7
|
||||
RegisterXMM7,
|
||||
RegisterXMM8,
|
||||
RegisterXMM9,
|
||||
RegisterXMM10,
|
||||
RegisterXMM11,
|
||||
RegisterXMM12,
|
||||
RegisterXMM13,
|
||||
RegisterXMM14,
|
||||
RegisterXMM15,
|
||||
};
|
||||
|
||||
class LogicalAddress {
|
||||
|
|
@ -444,6 +521,7 @@ public:
|
|||
String to_string_o8(Instruction const&) const;
|
||||
String to_string_o16(Instruction const&) const;
|
||||
String to_string_o32(Instruction const&) const;
|
||||
String to_string_o64(Instruction const&) const;
|
||||
String to_string_fpu_reg() const;
|
||||
String to_string_fpu_mem(Instruction const&) const;
|
||||
String to_string_fpu_ax16() const;
|
||||
|
|
@ -458,6 +536,7 @@ public:
|
|||
bool is_register() const { return m_register_index != 0x7f; }
|
||||
|
||||
unsigned register_index() const { return m_register_index; }
|
||||
RegisterIndex64 reg64() const { return static_cast<RegisterIndex64>(register_index()); }
|
||||
RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
|
||||
RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
|
||||
RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
|
||||
|
|
@ -507,11 +586,11 @@ private:
|
|||
String to_string_a64() const;
|
||||
|
||||
template<typename InstructionStreamType>
|
||||
void decode(InstructionStreamType&, AddressSize);
|
||||
void decode(InstructionStreamType&, AddressSize, bool has_rex_r, bool has_rex_x, bool has_rex_b);
|
||||
template<typename InstructionStreamType>
|
||||
void decode16(InstructionStreamType&);
|
||||
template<typename InstructionStreamType>
|
||||
void decode32(InstructionStreamType&);
|
||||
void decode32(InstructionStreamType&, bool has_rex_r, bool has_rex_x, bool has_rex_b);
|
||||
template<typename CPU>
|
||||
LogicalAddress resolve16(const CPU&, Optional<SegmentRegister>);
|
||||
template<typename CPU>
|
||||
|
|
@ -613,6 +692,8 @@ public:
|
|||
u8 cc() const { return has_sub_op() ? m_sub_op & 0xf : m_op & 0xf; }
|
||||
|
||||
AddressSize address_size() const { return m_address_size; }
|
||||
OperandSize operand_size() const { return m_operand_size; }
|
||||
ProcessorMode mode() const { return m_mode; }
|
||||
|
||||
String to_string(u32 origin, SymbolProvider const* = nullptr, bool x32 = true) const;
|
||||
|
||||
|
|
@ -625,6 +706,7 @@ private:
|
|||
StringView reg8_name() const;
|
||||
StringView reg16_name() const;
|
||||
StringView reg32_name() const;
|
||||
StringView reg64_name() const;
|
||||
|
||||
InstructionDescriptor* m_descriptor { nullptr };
|
||||
mutable MemoryOrRegisterReference m_modrm;
|
||||
|
|
@ -638,9 +720,14 @@ private:
|
|||
u8 m_rep_prefix { 0 };
|
||||
OperandSize m_operand_size { OperandSize::Size16 };
|
||||
AddressSize m_address_size { AddressSize::Size16 };
|
||||
ProcessorMode m_mode { ProcessorMode::Protected };
|
||||
bool m_has_lock_prefix : 1 { false };
|
||||
bool m_has_operand_size_override_prefix : 1 { false };
|
||||
bool m_has_address_size_override_prefix : 1 { false };
|
||||
bool m_has_rex_w : 1 { false };
|
||||
bool m_has_rex_r : 1 { false };
|
||||
bool m_has_rex_x : 1 { false };
|
||||
bool m_has_rex_b : 1 { false };
|
||||
};
|
||||
|
||||
template<typename CPU>
|
||||
|
|
@ -723,7 +810,7 @@ ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, Segmen
|
|||
u32 index = 0;
|
||||
switch (m_sib_index) {
|
||||
case 0 ... 3:
|
||||
case 5 ... 7:
|
||||
case 5 ... 15:
|
||||
index = cpu.const_gpr32((RegisterIndex32)m_sib_index).value();
|
||||
break;
|
||||
case 4:
|
||||
|
|
@ -734,7 +821,7 @@ ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, Segmen
|
|||
u32 base = m_displacement32;
|
||||
switch (m_sib_base) {
|
||||
case 0 ... 3:
|
||||
case 6 ... 7:
|
||||
case 6 ... 15:
|
||||
base += cpu.const_gpr32((RegisterIndex32)m_sib_base).value();
|
||||
break;
|
||||
case 4:
|
||||
|
|
@ -752,7 +839,6 @@ ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, Segmen
|
|||
break;
|
||||
default:
|
||||
VERIFY_NOT_REACHED();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -920,21 +1006,29 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
: m_operand_size(operand_size)
|
||||
, m_address_size(address_size)
|
||||
{
|
||||
VERIFY(operand_size != OperandSize::Size64);
|
||||
// Use address_size as the hint to switch into long mode, m_address_size refers to the default
|
||||
// size of displacements/immediates, which is 32 even in long mode, with the exception of moffset (see below).
|
||||
if (address_size == AddressSize::Size64) {
|
||||
m_operand_size = OperandSize::Size32;
|
||||
m_address_size = AddressSize::Size64;
|
||||
m_mode = ProcessorMode::Long;
|
||||
}
|
||||
u8 prefix_bytes = 0;
|
||||
for (;; ++prefix_bytes) {
|
||||
u8 opbyte = stream.read8();
|
||||
if (opbyte == Prefix::OperandSizeOverride) {
|
||||
if (operand_size == OperandSize::Size32)
|
||||
if (m_operand_size == OperandSize::Size32)
|
||||
m_operand_size = OperandSize::Size16;
|
||||
else if (operand_size == OperandSize::Size16)
|
||||
else if (m_operand_size == OperandSize::Size16)
|
||||
m_operand_size = OperandSize::Size32;
|
||||
m_has_operand_size_override_prefix = true;
|
||||
continue;
|
||||
}
|
||||
if (opbyte == Prefix::AddressSizeOverride) {
|
||||
if (address_size == AddressSize::Size32)
|
||||
if (m_address_size == AddressSize::Size32)
|
||||
m_address_size = AddressSize::Size16;
|
||||
else if (address_size == AddressSize::Size16)
|
||||
else if (m_address_size == AddressSize::Size16)
|
||||
m_address_size = AddressSize::Size32;
|
||||
m_has_address_size_override_prefix = true;
|
||||
continue;
|
||||
|
|
@ -947,6 +1041,15 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
m_has_lock_prefix = true;
|
||||
continue;
|
||||
}
|
||||
if (m_mode == ProcessorMode::Long && (opbyte & Prefix::REX_Mask) == Prefix::REX_Base) {
|
||||
m_has_rex_w = opbyte & 8;
|
||||
if (m_has_rex_w)
|
||||
m_operand_size = OperandSize::Size64;
|
||||
m_has_rex_r = opbyte & 4;
|
||||
m_has_rex_x = opbyte & 2;
|
||||
m_has_rex_b = opbyte & 1;
|
||||
continue;
|
||||
}
|
||||
auto segment_prefix = to_segment_prefix(opbyte);
|
||||
if (segment_prefix.has_value()) {
|
||||
m_segment_prefix = (u8)segment_prefix.value();
|
||||
|
|
@ -956,11 +1059,14 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
break;
|
||||
}
|
||||
|
||||
u8 table_index = to_underlying(m_operand_size);
|
||||
if (m_mode == ProcessorMode::Long && m_operand_size == OperandSize::Size32)
|
||||
table_index = to_underlying(OperandSize::Size64);
|
||||
if (m_op == 0x0f) {
|
||||
m_sub_op = stream.read8();
|
||||
m_descriptor = &s_0f_table[to_underlying(m_operand_size)][m_sub_op];
|
||||
m_descriptor = &s_0f_table[table_index][m_sub_op];
|
||||
} else {
|
||||
m_descriptor = &s_table[to_underlying(m_operand_size)][m_op];
|
||||
m_descriptor = &s_table[table_index][m_op];
|
||||
}
|
||||
|
||||
if (m_descriptor->format == __SSE) {
|
||||
|
|
@ -977,13 +1083,21 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
|
||||
if (m_descriptor->has_rm) {
|
||||
// Consume ModR/M (may include SIB and displacement.)
|
||||
m_modrm.decode(stream, m_address_size);
|
||||
m_modrm.decode(stream, m_address_size, m_has_rex_r, m_has_rex_x, m_has_rex_b);
|
||||
m_register_index = m_modrm.reg();
|
||||
} else {
|
||||
if (has_sub_op())
|
||||
m_register_index = m_sub_op & 7;
|
||||
else
|
||||
m_register_index = m_op & 7;
|
||||
if (m_has_rex_b)
|
||||
m_register_index |= 8;
|
||||
}
|
||||
|
||||
if (m_mode == ProcessorMode::Long && (m_descriptor->long_mode_force_64 || m_descriptor->long_mode_default_64)) {
|
||||
m_operand_size = OperandSize::Size64;
|
||||
if (!m_descriptor->long_mode_force_64 && m_has_operand_size_override_prefix)
|
||||
m_operand_size = OperandSize::Size32;
|
||||
}
|
||||
|
||||
bool has_slash = m_descriptor->format == MultibyteWithSlash;
|
||||
|
|
@ -1010,8 +1124,22 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
return;
|
||||
}
|
||||
|
||||
auto imm1_bytes = m_descriptor->imm1_bytes_for_address_size(m_address_size);
|
||||
auto imm2_bytes = m_descriptor->imm2_bytes_for_address_size(m_address_size);
|
||||
// 2.2.1.3 Direct Memory-Offset MOVs
|
||||
auto effective_address_size = m_address_size;
|
||||
if (m_mode == ProcessorMode::Long) {
|
||||
switch (m_descriptor->format) {
|
||||
case OP_AL_moff8: // A0 MOV AL, moffset
|
||||
case OP_EAX_moff32: // A1 MOV EAX, moffset
|
||||
case OP_moff8_AL: // A2 MOV moffset, AL
|
||||
case OP_moff32_EAX: // A3 MOV moffset, EAX
|
||||
effective_address_size = AddressSize::Size64;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
auto imm1_bytes = m_descriptor->imm1_bytes_for(effective_address_size, m_operand_size);
|
||||
auto imm2_bytes = m_descriptor->imm2_bytes_for(effective_address_size, m_operand_size);
|
||||
|
||||
// Consume immediates if present.
|
||||
switch (imm2_bytes) {
|
||||
|
|
@ -1024,6 +1152,9 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
case 4:
|
||||
m_imm2 = stream.read32();
|
||||
break;
|
||||
case 8:
|
||||
m_imm2 = stream.read64();
|
||||
break;
|
||||
default:
|
||||
VERIFY(imm2_bytes == 0);
|
||||
break;
|
||||
|
|
@ -1039,6 +1170,9 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
case 4:
|
||||
m_imm1 = stream.read32();
|
||||
break;
|
||||
case 8:
|
||||
m_imm1 = stream.read64();
|
||||
break;
|
||||
default:
|
||||
VERIFY(imm1_bytes == 0);
|
||||
break;
|
||||
|
|
@ -1055,7 +1189,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, OperandSiz
|
|||
}
|
||||
|
||||
template<typename InstructionStreamType>
|
||||
ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, AddressSize address_size)
|
||||
ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stream, AddressSize address_size, bool has_rex_r, bool has_rex_x, bool has_rex_b)
|
||||
{
|
||||
u8 mod_rm_byte = stream.read8();
|
||||
m_mod = mod_rm_byte >> 6;
|
||||
|
|
@ -1063,7 +1197,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
|
|||
m_rm = mod_rm_byte & 7;
|
||||
|
||||
if (address_size == AddressSize::Size32) {
|
||||
decode32(stream);
|
||||
decode32(stream, has_rex_r, has_rex_x, has_rex_b);
|
||||
switch (m_displacement_bytes) {
|
||||
case 0:
|
||||
break;
|
||||
|
|
@ -1118,8 +1252,10 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode16(InstructionStreamType&)
|
|||
}
|
||||
|
||||
template<typename InstructionStreamType>
|
||||
ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& stream)
|
||||
ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& stream, bool has_rex_r, bool has_rex_x, bool has_rex_b)
|
||||
{
|
||||
m_reg |= has_rex_r << 3;
|
||||
|
||||
switch (m_mod) {
|
||||
case 0b00:
|
||||
if (m_rm == 5) {
|
||||
|
|
@ -1134,6 +1270,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& st
|
|||
m_displacement_bytes = 4;
|
||||
break;
|
||||
case 0b11:
|
||||
m_rm |= has_rex_b << 3;
|
||||
m_register_index = rm();
|
||||
return;
|
||||
}
|
||||
|
|
@ -1142,8 +1279,8 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& st
|
|||
if (m_has_sib) {
|
||||
u8 sib_byte = stream.read8();
|
||||
m_sib_scale = sib_byte >> 6;
|
||||
m_sib_index = (sib_byte >> 3) & 7;
|
||||
m_sib_base = sib_byte & 7;
|
||||
m_sib_index = (has_rex_x << 3) | ((sib_byte >> 3) & 7);
|
||||
m_sib_base = (has_rex_b << 3) | (sib_byte & 7);
|
||||
if (m_sib_base == 5) {
|
||||
switch (mod()) {
|
||||
case 0b00:
|
||||
|
|
@ -1159,6 +1296,8 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& st
|
|||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
}
|
||||
} else {
|
||||
m_rm |= has_rex_b << 3;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue