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Kernel: Hide the implementation detail that MSRs use two registers
When retrieving and setting x86 MSRs two registers are required. The existing setter and getter for the MSR class made this implementation detail visible to the caller. This changes the setter and getter to use u64 instead.
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04a912f68f
Notes:
sideshowbarker
2024-07-18 10:31:57 +09:00
Author: https://github.com/gunnarbeutner Commit: https://github.com/SerenityOS/serenity/commit/04a912f68fa Pull-request: https://github.com/SerenityOS/serenity/pull/8414
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@ -30,15 +30,19 @@ public:
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{
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}
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void get(u32& low, u32& high)
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[[nodiscard]] u64 get()
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{
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u32 low, high;
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asm volatile("rdmsr"
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: "=a"(low), "=d"(high)
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: "c"(m_msr));
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return ((u64)high << 32) | low;
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}
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void set(u32 low, u32 high)
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void set(u64 value)
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{
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u32 low = value & 0xffffffff;
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u32 high = value >> 32;
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asm volatile("wrmsr" ::"a"(low), "d"(high), "c"(m_msr));
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}
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};
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@ -1128,7 +1128,7 @@ UNMAP_AFTER_INIT void Processor::gdt_init()
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#if ARCH(X86_64)
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MSR gs_base(MSR_GS_BASE);
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gs_base.set((size_t)this & 0xffffffff, (size_t)this >> 32);
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gs_base.set((u64)this);
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#else
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asm volatile(
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"mov %%ax, %%ds\n"
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@ -136,18 +136,15 @@ UNMAP_AFTER_INIT void APIC::initialize()
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PhysicalAddress APIC::get_base()
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{
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u32 lo, hi;
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MSR msr(APIC_BASE_MSR);
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msr.get(lo, hi);
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return PhysicalAddress(lo & 0xfffff000);
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auto base = msr.get();
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return PhysicalAddress(base & 0xfffff000);
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}
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void APIC::set_base(const PhysicalAddress& base)
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{
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u32 hi = 0;
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u32 lo = base.get() | 0x800;
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MSR msr(APIC_BASE_MSR);
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msr.set(lo, hi);
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msr.set(base.get() | 0x800);
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}
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void APIC::write_register(u32 offset, u32 value)
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